IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 12

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set
HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for a timing
diagram illustration of parallel programming of the flag offset values.
INTERSPERSED PARITY
Table 1 for the setup configuration of Interspersed Parity. The Interspersed
Parity function allows the user to select the location of the parity bits in the word
loaded into the parallel port (A0-An) during programming of the flag offset values.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
TABLE 3 — PORT B ENABLE FUNCTION TABLE
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit. If Interspersed Parity is selected
serial programming of the offset values is not permitted, only parallel program-
ming can be done.
— SERIAL LOAD
with FS2 LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
transition of MRS1 and MRS2. After this reset is complete, the X and Y register
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. There are 56-, 60-, or 64-
bit writes needed to complete the programming for the IDT72V3684, IDT72V3694,
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset
Interspersed Parity is selected during a Master Reset of the FIFO. Refer to
CSB
CSA
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W/RA
W/RB
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
ENB
ENA
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
MBB
MBA
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
CLKB
CLKA
↑
↑
↑
↑
X
X
↑
↑
X
↑
X
↑
X
X
X
X
TM
WITH
12
or IDT72V36104, respectively. The four registers are written in the order Y1,
X1, Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1
register and the last-bit write stores the least significant bit of the X2 register. Each
register value can be programmed from 1 to 16,380 (IDT72V3684), 1 to 32,764
(IDT72V3694), or 1 to 65,532 (IDT72V36104).
Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/
Data B (B0-B35) I/O
IRB) flag also remains LOW throughout the serial programming process, until
all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition
of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure 6
for Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset
Values (IDT Standard and FWFT Modes) timing diagram.
FIFO WRITE/READ OPERATION
(CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both CSA and W/RA are LOW.
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
Data A (A0-A35) I/O
When the option to program the offset registers serially is chosen, the Port A
The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
High-Impedance
High-Impedance
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
COMMERCIAL TEMPERATURE RANGE
Mail2 read (set MBF2 HIGH)
Mail1 read (set MBF1 HIGH)
Port Function
Port Function
FIFO2 write
FIFO1 write
FIFO2 read
FIFO1 read
Mail1 write
Mail2 write
None
None
None
None
None
None
None
None