IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 25

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. If Port B size is word or byte, t
A0-A35
B0-B35
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
W/RA
If the time between the CLKB edge and the rising CLKA edge is less than t
cycle later than shown.
W/RB
CLKA
CLKB
SKEW1
MBA
MBB
ORA
CSA
CSB
ENB
ENA
IRB
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
FIFO2 Empty
LOW
LOW
HIGH
LOW
LOW
LOW
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
W1
Old Data in FIFO2 Output Register
t
SKEW1
t
t
t
ENH
DH
ENH
(1)
t
CLKH
1
t
CLK
SKEW1
t
CLKL
TM
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
t
CLKH
WITH
25
2
t
CLK
t
REF
3
t
A
t
CLKL
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
4677 drw19