IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 26

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. If Port B size is word or byte, t
A0-A35
B0-B35
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
CLKA edge is less than t
W/RA
CLKB
W/RB
CLKA
SKEW1
MBA
MBB
ENB
CSA
CSB
EFA
ENA
FFB
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
LOW
t
t
ENS2
ENS2
SKEW1
t
DS
Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
SKEW1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
W1
t
SKEW1
t
t
t
ENH
ENH
DH
(1)
t
CLKH
1
t
CLK
t
CLKL
TM
WITH
t
26
2
REF
t
CLKH
t
ENS2
t
CLK
t
CLKL
t
REF
t
A
t
ENH
COMMERCIAL TEMPERATURE RANGE
W1
4677 drw20