IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 28

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
A0-A35
B0-B35
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
CLKA
W/RA
CLKB
W/RB
CLKB edge is less than t
SKEW1
MBA
ORA
MBB
ENA
ENB
CSA
CSB
IRB
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
FIFO2 FULL
LOW
LOW
LOW
LOW
HIGH
LOW
Previous Word in FIFO2 Output Register
t
CLKH
SKEW1
t
CLK
, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
t
ENS2
t
CLKL
t
t
SKEW1
ENH
t
A
(1)
1
t
CLKH
TM
WITH
t
CLK
28
t
CLKL
2
Next Word From FIFO2
t
WFF
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
Write
t
t
DH
WFF
t
t
ENH
ENH
4677 drw23