AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 11

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

1.1 AD1836 Serial Port Clocks And Frame Sync Rates
To keep clock jitter to a minimum, the AD1836 derives its clock internally from an externally attached 12.288 MHz crystal
(24.576 MHz if generating 96 kHz sample rates) and drives a buffered clock to the ADSP-21161 over the serial link under the
signal name ABCLK. Clock jitter at the AD1836 DACs and ADCs is a fundamental impediment to high quality output, and
the internally generated clock provided the AD1836 with a clean clock that is independent of the physical proximity of the
ADSP-21161 processor. ABCLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 8, 32-bit
outgoing and incoming time slots with a selected sample rate of 48 kHz. The TDM serial data is transitioned on each rising
edge of ABCLK. The receiver of TDM data, AD1836 for outgoing data and the ADSP-21161 for incoming data, samples each
serial bit on the falling edges of ABCLK. The AD1836 drives the serial bit clock at 12.288 MHz, which the ADSP-21161 then
qualifies with a synchronization signal to construct audio frames.
The beginning of all audio sample packets, or “Audio Frames”, transferred over the TDM link is synchronized to the rising
edge of the FSTDM (ALRCLK) signal. In TDM mode, the ALRCLK pin is renamed as the FSTDM pin. The FSTDM
(ALRCLK) pin is used for the serial interface frame synchronization and is generated by the AD1836 as an input to the ADSP-
21161. Synchronization of all TDM data transactions is signaled by the ADSP-21161 via the FS0 signal. FSTDM, fixed at 48
kHz, is derived by dividing down the serial bit clock (ABCLK). The ADSP-21161 takes SCLK0 (ABCLK) and FS0 (FSTDM)
as inputs. A frame sync is generated once every 256 SCLK0 cycles, which yields a 48kHz FSTDM signal whose period defines
an audio frame. The FSTDM (FS0) pulse is driven by the AD1836 codec. To accept both an externally generated 48 kHz
frame sync with an externally generated 12.288 MHz SCLK, the DSP must the corresponding bits to a 1 in the SPCTL registers
to accept these externally generated signals. The AD1836's frame rate is always equivalent to the sample rate of operation, i.e.,
a 48 kHz frame rate means we are transmitting and receiving audio data at a rate of a 48 kHz sample rate.
The ASDATA1 and DSDATA1 pins handle the serial data input and output of the AD1836. Both the AD1836’s ASDATA1
and DSDATA1 pins transmit or receive data on 8 different timeslots per audio frame. The AD1836 transmits data on every
rising edge of ABCLK (SCLK0) and it samples received data on the falling edge of ABCLK (SCLK0).