AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 41

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

6.1 ADSP-21161 SPORT DMA & AD1836 Multichannel Timing Notes
Depending on processing data from the SPORT2 transmit interrupt or SPORT0 receive interrupt, the DSP programmer should
be aware of TX/RX serial interrupt timing differences. If we process data from the SPORT2 transmit interrupt, the DSP will
process incoming rx data in the current frame for timeslots 0 to 5. However, current audio frame timeslots 6 and 7 may not be
processed until the received audio frame or next transmit interrupt. Similarly, if we process data using the SPORT0 receive
interrupt, tx DMA data for timeslots 0 and 1 have already been transferred from the transmit DMA buffers into the SPORT tx
FIFO "queue", so the newly processed data for slots 0 and 1 will not be transmitted until the next audio frame.
The reason for this difference is because when using SPORT TX and RX DMA chaining in TDM mode, the DMA interrupts
are always at least two timeslots apart (See Figure 28 below). This is because the Transmit TCB initially places the first two
words from the tx DMA buffer into the SPORT1 TX buffer registers. This automatically decrements the Transmit DMA count
register by two. After the assertion of the TX chained-DMA interrupt, the data for channels 6 and 7 have not been DMA'ed into
internal memory yet.
Thus, before timeslot 0 even begins transmit/receive activity, the RX DMA Count = 8 while the TX DMA Count = 6
(assuming we have declared 8-word TX and RX DMA buffers with 8 active timeslots enabled on the serial port). The transmit
interrupt occurs when the TX DMA Count = 0, and this interrupt request occurs on the second DSP clock cycle immediately
after the LSB of timeslot 5 is transmitted. While this transmit interrupt is generated, the transmit data for the AD1836 right
channel DAC3 timeslot is currently shifting out of the SPORT's Tx-shift register in slot 6, while the AD1836 right auxiliary
DAC channel (AD1852 right) data for channel 7 is in the TX2A register queue, waiting to be transmitted after timeslot 6 data is
finished shifting out of the SPORT. After both the transmit and receive interrupts are latched in the current frame [after
timeslots 5(tx) or 7(rx)], the TCBs will be reloaded, and then DMA internal memory transfers will.
These DMA timing differences are important to know, however they are not catastrophic for the DSP system designer. Since
the AD1836 does not contain control, register or valid tag information on timeslot like AC-97 codecs (which are severely
affected by these DMA timing differences), the audio frame latency issues for the AD1836 are not a problem, since user's
cannot perceive an audio delay of one 48 KHz sample between the input from the AD1836 to SPORT0, and the output of
SPORT2 to the AD1836.
Figure 28. AD1836/SPORT Timeslot, DMA Count and RX & TX Interrupt Timing Relationships
FSTDM
D0A
C0A
(DMA RX Count Reg)
D2A
C3A
(DMA TX Count Reg)
[TX queue reloaded with 1
of SPORT1]
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(1 / 12.288 MHz SCLK) x (32-bits/timeslot) x (2 timeslots) = 5.208 microseconds
1 / 100 MHz Instruction Execution = 10 nanoseconds per instruction
5.208 microseconds / 10 nanoseconds = 156.25 = 521 DSP CCLK cycles TX/RX DMA IRQ difference
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< SLOT0 >< SLOT1 >< SLOT2 >< SLOT3 >< SLOT4 >< SLOT5 >< SLOT6 >< SLOT7 >
8
< SLOT0 >< SLOT1 >< SLOT2 >< SLOT3 >< SLOT4 >< SLOT5 >< SLOT6 >< SLOT7 >
6
7
5
st
two tx_buf values after TCB download as slots 6 and 7 are shifted out
6
4
5
3
2
4
3
1
2
0
TX IRQ Here
1
0
RX IRQ Here
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