AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 50

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

//
SPORT_DMAs_not_done_yet:
Wait_Approx_1500ms:
waitloop250ms:
/* This loop has been cut to approx length 110ms instead of 167ms*/
Wait_Approx_167ms:
waitloop200ms:
/////////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////////
Count_SPORT1_RX_IRQs:
Count_SPORT3_TX_IRQs:
SPORT1 and SPORT3 Interrupt Service Routines
/* With lcntr = 1000, this actually waits roughly 1s*/
r0=dm(SP1I_counter);
r0=r0+1;
dm(SP1I_counter)=r0;
RTI;
r0=dm(SP3I_counter);
r0=r0+1;
dm(SP3I_counter)=r0;
RTI;
14
13
12
11
10
NOTE: SPORT1 & SPORT3 clock and frame syncs tied together, generated by SPORT3 */
R0 = 0x000330F1;
bit set ustat2 SDEN_A | LAFS | LFS | FSR | CKRE | SLEN16 | SPEN_A;
bit clr ustat2 DDIR | IFS | ICLK;
dm(SPCTL1) = ustat2;
bit set imask SP1I | SP3I;
idle;
R1 = 0x0000000A;
R0 = DM(DMASTAT);
R0 = R0 AND R1;
IF NE jump SPORT_DMAs_not_done_yet;
bit clr ustat1 0xFFFFFFFF;
dm(SPCTL1) = ustat1;
dm(SPCTL3) = ustat1;
IRPTL=0;
bit clr IMASK SP1I | SP3I;
rts;
lcntr = 1000, do waitloop250ms until lce;
nop;
rts;
lcntr = 110, do waitloop200ms until lce;
nop;
rts;
9
8:4
3
2:1
0
nop;
//call Wait_Approx_999us;
nop;
nop;
nop;
nop;
//call Wait_Approx_999us;
nop;
nop;
nop;
-- IRFS - RFS Source: 0 external
-- RFS Requirement:
-- Active Clock Edge:
-- Operation mode:
-- Rcv Clk source:
-- 16/32-bit pack:
-- Serial Word Length minus 1:
-- Endian word format:
-- Data Type:
-- SPORT Enable A:
nop;
nop;
nop;
nop;
nop;
nop;
0:0 r-justify; fill MSBs w/0s
/* get last count */
/* increment count */
/* save updated count */
/* get last count */
/* increment count */
/* save updated count */
0 non-I2S mode
0 external
0 no packing of received 16-bit words into 32-bit words
1 enable A
1 RFS required
// enable SPORT0 RX and SPORT2 TX interrupts
// Test for SPORT1 and SPORT3 DMA completion
// disable SPORT1 and SPORT3 interrupts
1 rising edge
0 MSB first
//
//
//
01111