AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 59

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

C code for DSP System & Codec Initialization Routines
#include "ADDS_21161_EzKit.h"
#include <def21161.h>
#include <signal.h>
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int
int powerdown_rx_buf0a[4]; // rx dma dummy buffer not used for anything;
//
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#define TX_BUF3A_LEN
int tx_buf3a[TX_BUF3A_LEN] = //program register commands
rx0a_buf[8] - DSP SPORT recieve buffer
Slot # Description
------ --------------------------------------
0
1
2
3
4
5
6
7
tx2a_buf[8] - DSP SPORT transmit buffer
Slot # Description
------ --------------------------------------
0
1
2
3
4
5
6
7
This Serial Port 0 Recieve Interrupt Service Routine performs arithmetic computations on
the SPORT1 receive DMA buffer (rx_buf) and places results to SPORT1 transmit DMA buffer (tx_buf)/
Receives input data from the 2 AD1836 ADCs via SPORT1 and transmits processed audio data
back out to the 3 AD1836 Stereo DACs/Line Outputs
powerdown_AD1836[4] = {DAC_CONTROL1 | WRITE_REG | 0x004,
AD1836 codec register commands - Serial SPI 16-bit Word Format as follows:
{DAC_CONTROL1 | WRITE_REG | 0x000,
DAC_CONTROL1 | WRITE_REG | 0x000,
DAC_CONTROL2 | WRITE_REG | 0x000,
DAC_VOLUME0
DAC_VOLUME1
DAC_VOLUME2
DAC_VOLUME3
DAC_VOLUME4
DAC_VOLUME5
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL3 | WRITE_REG | 0x000,
ADC_CONTROL2 | WRITE_REG | 0x380,
Internal ADC 0 Left Channel
Internal ADC 1 Left Channel
External Auxilliary ADC 0 Left Chan.
External Auxilliary ADC 1 Left Chan.
Internal ADC 1 Right Channel
Internal ADC 1 Right Channel
External Auxilliary ADC 0 Right Chan.
External Auxilliary ADC 1 Right Chan.
Internal DAC 0 Left Channel
Internal DAC 1 Left Channel
Internal DAC 2 Left Channel
External Auxilliary DAC 0 Left Chan.
Internal DAC 0 Right Channel
Internal DAC 1 Right Channel
Internal DAC 2 Left Channel
External Auxilliary DAC 0 Right Chan.
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
D15 to D12
D11
D10
D9 to D0
21
AD1836 - SETUP and Data Routing
DAC_CONTROL1 | WRITE_REG | 0x004,
ADC_CONTROL1 | WRITE_REG | 0x080,
ADC_CONTROL1 | WRITE_REG | 0x080};
= Codec Register Address
= Read/Write register (1=rd, 0=wr
= reserved bit, clear to zero
= Data Field for codec register
// we "OR" in address, rd/wr, and register data
// for ease in reading register values
// write DAC_CTL1 twice to workaround pwdwn SPI anomaly
// write ADC_CTL1 twice to workaround pwdwn SPI anomaly
// 256*Fs Clock Mode !!!, differential PGA mode
// SOUT MODE = 110 --> TDM Mode, Master device
DSP Data Memory Address
-----------------------------------------------
DM(rx0a_buf + 0) = DM(rx0a_buf + Internal_ADC_L0) /
DM(rx0a_buf + 1) = DM(rx0a_buf + Internal_ADC_L1) /
DM(rx0a_buf + 2) = DM(rx0a_buf + AUX_ADC_L0)
DM(rx0a_buf + 3) = DM(rx0a_buf + AUX_ADC_L1)
DM(rx0a_buf + 4) = DM(rx0a_buf + Internal_ADC_R0) /
DM(rx0a_buf + 5) = DM(rx0a_buf + Internal_ADC_R1) /
DM(rx0a_buf + 6) = DM(rx0a_buf + AUX_DAC_R0)
DM(rx0a_buf + 7) = DM(rx0a_buf + AUX_DAC_R1)
DSP Data Memory Address
-----------------------------------------------
DM(tx0a_buf + 0) = DM(tx0a_buf + Internal_DAC_L0) /
DM(tx0a_buf + 1) = DM(tx0a_buf + Internal_DAC_L1) /
DM(tx0a_buf + 2) = DM(tx0a_buf + Internal_DAC_L2) /
DM(rx0a_buf + 3) = DM(tx0a_buf + AUX_DAC_L0)
DM(tx0a_buf + 4) = DM(tx0a_buf + Internal_DAC_R0) /
DM(tx0a_buf + 5) = DM(tx0a_buf + Internal_DAC_R1) /
DM(tx0a_buf + 6) = DM(tx0a_buf + Internal_DAC_R3) /
DM(tx0a_buf + 7) = DM(tx0a_buf + AUX_DAC_R0)
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