AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 28

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

In order to provide easier reading of the AD1836 DSP assembly driver, symbolic macro definitions are defined in order to
describe each offset in the DMA buffer, showing it's relationship to the actual TDM timeslot and AD1836 ADC/DAC resource.
These are defined as follows:
/*AD1836 TDM Timeslot Definitions */
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
The following figure 21 show the assembly declaration of the SPORT0 receive DMA buffer and the SPORT2 transmit DMA
buffer, as well as the symbolic offsets for all AD1836 internal and external auxiliary resources.
Figure 21: SPORT RX/TX DMA buffer timeslot representations
rx_buf0a[8]
tx_buf2a[8]
tx_buf2a + Internal_DAC_L0
tx_buf2a + Internal_DAC_L1
tx_buf2a + Internal_DAC_L2
tx_buf2a + AUX_DAC_L0
tx_buf2a + Internal_DAC_R0
tx_buf2a + Internal_DAC_R1
tx_buf2a + Internal_DAC_R1
tx_buf2a + AUX_DAC_R0
rx_buf0a + Internal_ADC_L0
rx_buf0a + Internal_ADC_L1
rx_buf0a + AUX_ADC_L0
rx_buf0a + AUX_ADC_L1
rx_buf0a + Internal_ADC_R0
rx_buf0a + Internal_ADC_R1
rx_buf0a + AUX_ADC_R0
rx_buf0a + AUX_ADC_R1
Internal_ADC_L0
Internal_ADC_L1
AUX_ADC_L0
AUX_ADC_L1
Internal_ADC_R0
Internal_ADC_R1
AUX_ADC_R0
AUX_ADC_R1
Internal_DAC_L0
Internal_DAC_L1
Internal_DAC_L2
AUX_DAC_L0
Internal_DAC_R0
Internal_DAC_R1
Internal_DAC_R2
AUX_DAC_R0
Timeslot #
0
1
2
3
4
5
6
7
Timeslot #
0
1
2
3
4
5
6
7
.segment /dm
.var
SPORT2 transmit DMA
buffer
.endseg;
.segment /dm
.var
SPORT1 receive DMA
buffer
.endseg;
tx_buf2a[8];
rx_buf0a[8];
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
dm_codec;
dm_codec;
//
//