AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 11

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

run
sleep 50
stop
# OK DDR is set up, now define an area for 16MB FLASH at
# 0xFF000000 - 0xFFFFFFFF. Note how we re-use the MASx registers
# again, once the previous TLB entry has been written.
writespr 624 0x10030000 # MAS0
writespr 625 0xc0000700 # MAS1
writespr 626 0xff00001A # MAS2
writespr 627 0xff000015 # MAS3
writespr 628 0x00000000 # MAS4
# write tlb entry
writereg PC 0xFFFFF000
run
sleep 50
stop
# The rest of the initialization follows on from here…
2.3.6 Core Reset
Book E–compliant cores do not share a common reset vector with the AIM version of the PowerPC
architecture. Due to the additional features and capabilities of the e500 core, the initialization process is
different. Unlike the AIM version of the PowerPC core, once execution begins, the e500 core is in virtual
mode with a hardware-initialized TLB entry.
In its default mode of operation, after Reset the e500 core always performs a fetch from address
0xFFFF_FFFC. The instruction obtained from this address must contain a branch to an address somewhere
within the last four Kbytes of the memory map. The most common address will be 0xFFFF_F000. The
initialization code that starts at this address will probably set up other entries in the MMU to enable other
address ranges in the memory map. It may also increase the size of the default TLB1 entry from four Kbytes
to cover the size of the boot ROM
As part of the power-on reset or hard reset process, some device functions are initialized by sampling a
number of signals during HRESET. These signals are normally pulled high or low by external resistors to
select the desired function. See Section 5, “Initialization, Reset and Boot Procedures,” for more information.
2.3.7 Branch Prediction
The e500 core does not implement the static branch prediction defined by the PowerPC architecture. It
implements dynamic branch prediction using 512-entry, 4-way set associative branch target buffer (BTB)
to maintain a history of branches that have been encountered and of how they have or have not been taken,
or not taken. Entries can be locked into the BTB under software control. Dynamic branch prediction can be
disabled in the branch unit control and status register (BUCSR), in which case, it predicts every branch as
not taken.
MOTOROLA
The PowerQUICC III has a number of boot options. These options are
user-defined during this HRESET/configuration phase and allow the
device to be booted from RapidIO, PCI, I
initialization and boot operation of the PowerQUICC III is covered in
more detail in Section 5, “Initialization, Reset and Boot Procedures.”
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
2
C Boot Sequencer etc. The reset,
Core Differences
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