AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 6

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Core Differences
Core Differences
The e500 core implements new instructions related to the signal processing engine (SPE) APU and to
support single-precision floating-point operations (SPFP APU).
Another, new APU is isel (Integer Select). This instruction performs a conditional register move operation
which helps to reduce the size of the code footprint and can avoid having to predict the outcome of a
condition and the use of conditional branches. It is also useful for conditional clearing of a register. In the
Book E architecture the isel is treated as an APU.
Another useful new supervisor instruction is wrtee[i]. This instruction manipulates the EE bit of the MSR
register and replaces several instructions required by the AIM architecture to perform the same task. The
advantage here is that wrtee[i] is used to update MSR[EE] without affecting any other MSR bits that may
have changed.
for example:
AIM architecture
mfmsr rn
mr ra,rn
andi ra,ra,0x7FFF
mtmsr ra
:
:
mtsr rn
2.3.2 Programming Model
The programming model of the e500 core is shown in Figure 4.
6
The SPE APU is supported only through the use of the libmoto library.
Section 5.3, “Boot Sequencer,” contains more information on the SPE and
the libmoto library.
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
; get MSR
;take a copy
;clear EE bit
;clear interrupt
; restore MSR
Go to: www.freescale.com
NOTE
e500 architecture
mfmsr rn
wrteei 0
:
:
wrtee rn
; get MSR
;clear interrupt
;restore MSR
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