AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 3

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Core Differences
2 Core Differences
The MPC8540 and MPC8560 devices implement the e500 core, which is based on a new embedded version
of the PowerPC architecture known as Book E. The following section describes the differences between the
e500 core and the 603e core used in PowerQUICC II devices.
2.1 Introduction
The e500 processor core is a low-power implementation of the family of reduced instruction set computing
(RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500
implements the 32-bit portion of the Book E architecture using the lower words in the 64-bit
general-purpose registers (GPRs).
Book E allows processors to provide auxiliary processing units (APUs), which are extensions to the
architecture. The most significant of these on the e500 is the signal processing engine APU (SPE APU),
which includes a suite of vector instructions that use the upper and lower halves of the GPRs as a single
two-element operand. Most APUs implemented on the e500 are defined by the Motorola Book E
implementation standards (EIS).
Like the 603e, the e500 provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and a
32-bit floating-point data type. The SPE APU on the e500 also supports signed and unsigned fractional data
types of 32 bits. The core complex is a superscalar processor that can issue two instructions and complete
two instructions per clock cycle. A block diagram of the core complex is shown in Figure 2. See
Section 2.3.1, “Instruction Set Differences” and Section 5.3, “Boot Sequencer,” for more information on
e500 APUs.
2.2 Key Features
™
The key features of the e500 core complex are detailed in the PowerPC
e500 Core Complex Reference
Manual and are not discussed in this application note.
MOTOROLA
Migrating from PowerQUICC II to PowerQUICC III
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