AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 13

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

3.1 CPM Performance & Internal Memory
To provide more available CPM bandwidth on the PowerQUICC III, the CPM operates at a maximum speed
of 333 MHz as opposed to 300 MHz on the PowerQUICC II (HiP7). This gives PowerQUICC III
applications a notable performance improvement over similar PowerQUICC II (HiP7) designs.
On both the PowerQUICC II (HiP7) and PowerQUICC III, 64 Kbytes of SRAM are available for both
instruction RAM and dual-port RAM (DPRAM). Figure 6 illustrates how the 32 Kbytes of instruction RAM
can be used to either store microcode patches, or as a general-purpose memory area for the e500 core.
Similarly, the 32 Kbytes of DPRAM can be used for CPM-RISC parameter RAM for storing data structures
and connection tables. Like the PowerQUICC II (HiP7) the PowerQUICC III can support eight microcode
trap registers. Similarly, both the PowerQUICC II (HiP7) and PowerQUICC III have 128 Kbytes of
ROM—an additional 68 Kbytes of ROM compared to the PowerQUICC II (HiP4).
3.2 Fast Communication Controllers
The PowerQUICC III CPM, like that of the PowerQUICC II, includes three full-duplex, fast serial
communication controllers (FCCs). Each controller can be used to support 10/100 BaseT Ethernet, 45 Mbps
HDLC (for example, up to E3/T3 rates) and transparent modes of operation. Both FCC1 and FCC2 can also
be used to support up to 155 Mbps (depending on the adaptation layer), 16/8-bit UTOPIA Level II ATM.
For this reason, the functionality and programming model of the FCC has remained unchanged between the
PowerQUICC II (HiP7) to PowerQUICC III.
3.3 Serial Communication and Management Channels
Figure 1 shows that the serial management channels (SMCs) that existed on the PowerQUICC II have been
removed from the PowerQUICC III. Instead, the SMC UART functionality can be implemented on the
faster serial communication channels (SCCs).
The function of each of the four SCCs is slightly different on the PowerQUICC III than on the
PowerQUICC II. On the PowerQUICC III, the 10 BaseT Ethernet support on the SCC has been removed
and that functionality is now provided through one of the three FCCs, or through one of the two three-speed
Ethernet controllers (TSECs), as shown in Table 2. Like the PowerQUICC II, the SCCs offer protocol
support for UART, HDLC, HDLC bus, Appletalk/Localtalk, transparent, and BISYNC modes. In order to
protect existing software legacy, the programming models for all of the supported protocols on the SCCs
are the same as the PowerQUICC II.
MOTOROLA
DMA (System)
DMA (Local)
e500 Core
CP (Data)
CP BTM
SMC GCI functionality is no longer supported on PowerQUICC III.
descriptors,
Data RAM
32 Kbytes
Dual-Port
Migrating from PowerQUICC II to PowerQUICC III
Buffers)
(Buffer
Freescale Semiconductor, Inc.
Figure 6. Internal CPM SRAM Configuration
For More Information On This Product,
Go to: www.freescale.com
Data
CP (Instruction)
NOTE
e500 Core
Communications Processor Module (CPM)
(Microcode)
Instruction
32 Kbytes
RAM
Data
CP Instruction
13