AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 32

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Summary
Summary
compare the Dhrystone benchmark for a standard optimized library then typically a value of 1.693
MIPS/MHz is obtained. Using the libmoto_e500 this performance can be considerably increased to 2.507
MIPS/MHz.
6.4 Migrating Between ADS platforms
Customers using the PowerQUICC I and II should already be familiar with the Application Development
Systems (or ADS) that is used for software/system bring-up. The PowerQUICC III continues this tradition
with the PQ3 ADS-Pilot board. This board enables all of the features of the PQ3 to be tested, for example,
TSEC, RapidIO, PCI, DDR, RS-232, and 10/100BaseT Ethernet.
We have already examined some of the considerations that must be taken into account when migrating
software from the PQ2 to the PQ3. In this section we will look at the necessary switch/jumper settings that
have to be made when testing code originally running on the PQ2ADS, onto a PQ3ADS-Pilot.
The PQ3ADS-Pilot board has a number of switches and jumpers in order to ensure maximum user
configurability. Please refer to the PowerQUICC III Application Development Systems Quick Reference
Guide supplied with your ADS board for full details and positioning of each switch.
6.5 Fast Ethernet Configuration
In order to enable Fast Ethernet (100BaseT) MII, legacy mode, the following jumpers should be set:
Each of the two fast Ethernet PHYs have an associated PHY address that must be defined in order to
correctly read and write to the MII. The respective PHY addresses for FETH2 and FETH3 are 0x02 and
0x03. In order to read and write to the MII, these addresses need to be set in the 5-bit PHY address field (bits
19–23) of the MII management address register (MIIMADD).
The fast Ethernet PHYs on the ADS-Pilot board use the Davicom DM9161 10/100 Mbps physical layer
transceiver chip. In order to allow the transceiver to auto negotiate properly, the following DM9161 registers
still need to be set:
reg 16. = 0x0610
Aux. config. set (De)Scrambler for normal operation.the (de)scrambler is configured to "bypass mode" by
the power-on reset latch
reg 00. = 0x1200
Control register autonegotiation enable/restart autonegotiation
7 Summary
This document has looked at the different aspects that existing PowerQUICC II users must consider when
migrating from PowerQUICC II to PowerQUICC III. Although a number of new system blocks, as well as
a new processor core, have been added onto the PowerQUICC III, we have hopefully shown that much of
32
•
•
•
•
•
•
SW4 [bit 5] Enable FETH2. Set this bit to ‘1’ position.
SW4 [bit 6] Enable FETH3. Set this bit to ‘1’ position.
Jumper 22 FETH2. Select ‘Legacy mode’. Position jumper between terminals 1 & 2.
Jumper 23 FETH3. Select ‘Legacy mode’. Position jumper between terminals 1 & 2.
Jumper 31 FETH2. Select ‘MII mode’. Position jumper between terminals 1 & 2.
Jumper 22 FETH3. Select ‘MII mode’. Position jumper between terminals 1 & 2.
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA