AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 22

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
4.5 On-Chip Network (OCeaN)
The on-chip network (OCeaN) is a 4-port, full crossbar switch fabric with 64-bit inbound/outbound
interfaces. Through each of the four ports, a total of 11 Gbyte/sec aggregated bandwidth can be supported
on the switch fabric (2.7 Gbyte/sec peak bandwidth per port).
This switch fabric has been designed in such a way as to be non-blocking through the use of pipelining,
transaction posting and priority traffic flows. Up to six different transactions can be posted into the fabric
before it stalls awaiting a transaction grant on the first one—enabling much more efficient use of the fabric.
Figure 11 shows the internal logic arrangement (consisting of wires and muxes) that make up the physical
on-chip network.
Under heavily loaded traffic conditions, traffic is prioritized in OCeaN using different traffic classes, some
of which have a higher priority than others. This allows higher priority traffic to make more forward
progress than lower priority traffic.
This latter point is the key mechanism by which processing deadlocks are avoided through the use of priority
reordering. For example, a request can be made from a presently blocked port, to another unblocked port in
order to pass a blocked transaction ahead. This helps to remove head-of-line blockages when switching
traffic between PCI/PCI-X, RapidIO, the DMA controller and the internal system bus.
4.6 Three-Speed Ethernet Controller
The three-speed Ethernet controller (TSEC) is a new hardware block on the PowerQUICC III (providing
Layer 1 & 2 functionality), allowing 10/100 & 1000BaseT Ethernet traffic to be transmitted and received.
Twin TSEC blocks are on both the MPC8540 and MPC8560 and are IEEE 802.3/3u/3x/3z and 802.3ac and
802.3ab specification compliant. Although both TSEC blocks are flexible enough to be programmed in
10/100/1000 BaseT and in MII, RMII, RGMII, TBI, RTBI modes, users should note that both the RGMII
and RTBI are 5V interfaces, all of the remaining interfaces are 3.3V. Power supply constraints mean that
users can only implement either 5V compliant interfaces or 3.3V interfaces—mixing different 5V/3.3V
interfaces is not a valid configuration.
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Figure 11. Internal Structure of On-Chip Network (OCeaN)
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
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Go to: www.freescale.com
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MOTOROLA