AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 19

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
4.2.1.4 Channel Continue/Halt/Abort
The DMA controller introduces three new channel control mechanisms, channel continue, halt and abort.
Channel continue is used in chaining. In basic mode, the current link address is re-fetched when the channel
is continued and in extended mode, the current list address is re-fetched. In the event that the last link or list
address has been reached, then the DMA will return to the channel halted state. It should be noted that even
when the channel is busy, it is possible to continue building new DMA descriptors by making use of the
channel continue feature as follows:
Channel abort is recognized by MR[CA]=1 and SR[CB]=0 and is used to finish the current sub-block
transfer and halt the relevant channel. Thus, channel halt, determined by SR[CB]=1, indicates that the DMA
engine has completed its current DMA transaction.
Another important feature with the PowerQUICC III DMA controller is that it can assign bandwidth on a
per channel basis—this prevents any single channel from consuming all of the DMA’s available data
bandwidth. Using bandwidth control allows a channel only to use its allotted bandwidth, after which, the
arbiter grants (round-robin) the next channel access to the shared resources.
4.2.1.5 Destination/Source Address Hold Enable
This feature is typically used in scenarios when reading or writing to some form of FIFO structure. If for
example an external device has a FIFO involved in the DMA process then multiple reads/writes will be
performed to the same address. In such a case, it is more efficient to hold the current source or destination
address and simply transfer a specific chunk of data. The transfer size is user specified through the source
and destination transfer size registers (MR[SAHTS] and MR[DAHTS] respectively).
4.3 Local Bus Controller
The local bus controller on the PowerQUICC III performs similar functions to the PowerQUICC II
implementation. The three main PowerQUICC II memory controller machines are still supported on the
PowerQUICC III:
Although functionally similar, the PowerQUICC III implementation of the UPM has three dedicated UPMs
unique to the local bus. On the PowerQUICC II, these UPMs also had to be shared with the 60x bus.
Similarly, on PowerQUICC II, the twelve available chip selects had to be shared with the 60x bus, on the
PowerQUICC III, there are eight dedicated chip selects specific to the local bus. The ability to support bank
based interleaving on the SDRAM controller that was on the PowerQUICC II has been removed. On the
SDRAM controller on the PowerQUICC III, only page-based interleaving is supported. The reason for this
is simple; Page-based interleaving allows a greater degree of flexibility and control when accessing
connected SDRAM devices.
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Set end of links/lists descriptor (EOLND/EOLSD)
Build new descriptor list
Clear EOLND/EOLSD
Restart DMA by issuing a Channel Continue (MR[CC])
GPCM—General-Purpose Chip Select Machine for classic memory interfaces such as SRAM
memory or FLASH.
UPM—User Programmable Machine that configures an internal timing generator to create
non-standard timings for peripheral devices.
SDRAM—Single Data Rate SDRAM controller allowing SDRAM devices to be gluelessly
connected.
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA