AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 15

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
4 New Features on PowerQUICC III
In addition to previously mentioned features, the PowerQUICC III also offers two integrated 10/100/1000
Ethernet controllers, a DDR SDRAM memory controller, a 64-bit PCI-X/PCI controller, and a RapidIO™
interconnect. This high level of integration simplifies board design and offers significant bandwidth and
performance for high-end control-plane and data-plane applications. New internal blocks such as 4-channel
hardware DMA engine, E500 coherency module (ECM) and non-blocking switch fabric (OCeaN), ensure
rapid transfer of data between all of the various peripheral modules and the outside communication network.
4.1 e500 Coherency Module (ECM)
At the heart of the PowerQUICC III is the ECM. The primary role of the ECM is to guarantee memory
coherency between the external memory interfaces (primarily DDR SDRAM) or memory on the local bus,
and the cache memory—either the L1 cache of the e500 core, or the L2 cache of the memory complex. If
an address falls into one of the ECM’s defined windows it is forwarded to the correct destination, for
example, if a buffer on the local bus is marked as snoopable, all traffic to that buffer will be routed using the
ECM. This ECM operation highlights the difference in the transaction style architecture of the
PowerQUICC III, when compared to the shared bus architecture of the PowerQUICC II.
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CPM Core, Memory
& Microcodes
Fast
Communication
Controllers
Serial
Communication
Controllers
Serial Management
Channels
Multi-Channel
Controllers
IDMA
SDMA
Configuration
Table 2. CPM Feature Comparison PowerQUICC II(HiP7) versus PowerQUICC III
CPM Block
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Transparent Mode
# Trap Registers
CPM Frequency
Instruction RAM
16-bit ATM UL2
Dual-Port RAM
Apple/Localtalk
8-bit ATM UL2
10/100 BaseT
10/100 BaseT
Programming
Transparent
Feature
Modes
HDLC
UART
HDLC
Model
(Max)
ROM
Go to: www.freescale.com
#
#
#
#
#
#
4 Virtual Channels
Big & Little Endian
(Using CPM B/W)
‘Traditional PQII’
PQII (HiP7)
300 MHz
45 Mbps
Yes (x3)
Yes (x4)
FCC1
FCC2
128K
32K
32K
Yes
Yes
Yes
Yes
Yes
8
3
4
2
2
2
4 DMA Hardware
‘Traditional PQII’
Big Endian Only
Not Supported
Not Supported
Implemented
PQIII (HiP7)
Channels
333 MHz
45 Mbps
Yes (x3)
FCC1
FCC2
128K
32K
32K
Yes
Yes
Yes
Yes
Yes
8
3
4
2
2
MOTOROLA