AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 20

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
New Features on PowerQUICC III
New Features on PowerQUICC III
The major difference between the two devices is that the local bus controller on the PowerQUICC III can
operate up to 166 MHz—the maximum supported frequency on the PowerQUICC II is 100 MHz. The local
bus on the PowerQUICC III runs with a fixed frequency referenced from the main system frequency,
SYSCLK. It should also be noted that the local bus controller runs synchronized with the CCB clock, hence
if you have the CCB running at 333 MHz then the frequency of the local bus is divided down from this to
either 2:1, 4:1 or 8:1. (Users should note that the 8:1 divide option is the default configuration from reset).
The local bus also has optimized state machines which are designed to support the specific transaction size
that is generated by the CPM. Hence, a 32-bit configured local bus will have minimal associated overhead
when passing traffic between external peripherals and the CPM.
The local bus programming model remains the same as the PowerQUICC II with it supporting 8 chip
selects, each individually configurable to either 8, 16 or 32 bits wide. Each individual chip-select is capable
of supporting up to 2 Gigabytes of address space. As before, the local bus supports both natural parity and
read-modify-write (RMW) data parity checking.
One difference with the local bus controller on the PowerQUICC III is that it is possible to select a wider
range of addressable banks within a connected device due to its 34-bit address decoding, as opposed to
32-bit address decoding on the PowerQUICC II. In order to save pins during the design of the
PowerQUICC III design, it was decided that a 32-bit multiplexed address/data interface would be
implemented. This is an important difference from the PowerQUICC II as any design will require an
external buffer and latch combination with which to demultiplex the muxed address/data signals. The logic
for controlling these external devices is integrated into the PowerQUICC III design. (On the
PowerQUICC II, the local bus had 18 separate address pins and 32 data pins).
4.4 Dual Data Rate (DDR) Memory Controller
The dual data rate (DDR) SDRAM controller is a new feature on the PowerQUICC III and currently
supports DDR Type 1 SDRAM up to 333 MHz—as DDR memory is clocked on both edges of the input
clock, the actual maximum clock rate is 167 MHz. (Users should note that the MCK# [5:0] signals are
simply the inverted clocks from the MCK [5:0] signals and not true differential clock signals.)
On the PowerQUICC II, the 60x bus allowed users to connect to SDRAM, Flash and other 60x bus
compatible peripherals. However on the PowerQUICC III, the DDR controller is a dedicated 64-bit data bus
(+ 8-bit ECC) with no external master capability and it is used exclusively for DDR memories as the main
system bus. Users should note that connection to other external masters can be readily implemented through
either the PCI or RapidIO interfaces.
4.4.1 Feature Summary
The DDR controller is capable of supporting discrete or DIMM DDR memories between 64 Mbit and 1 Gbit
in size. The DDR controller has four chip selects that can be used to access a (theoretical) maximum of
1gigabyte addressing space. It should be noted that in reality users cannot use the full 4 gigabytes for DDR,
since 4 gigabytes is the maximum addressing that the whole PowerQUICC III can handle. Thus, the DDR
controller has been restricted through design to have a maximum addressing limit of 3.5 gigabytes to allow
other connected peripherals to have space in the PowerQUICC III memory map.
4.4.2 DLL Delay Compensation Loop
Since the PowerQUICC III operates at much higher frequencies than the PowerQUICC II, the clocks for the
memory interface (the Digital Locked Loops or DLLs) have been integrated into the PowerQUICC III
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Migrating from PowerQUICC II to PowerQUICC III
MOTOROLA
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