IDT72V3680L10PF IDT, Integrated Device Technology Inc, IDT72V3680L10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V3680L10PF
• Description: IC FIFO SS 16384X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3680L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3680L10PF

PIN CONFIGURATIONS
DESCRIPTION:
exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories
with clocked read and write controls and a flexible Bus-Matching x36/x18/x9
data flow. These FIFOs offer several key user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 1 Mbit
NOTE:
1. DNC = Do Not Connect.
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
empty FIFO to the time it can be read, is fixed and short.
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 are
INDEX
DNC
DNC
GND
WEN
GND
GND
GND
SEN
D30
D28
D27
V
D32
V
D22
V
D19
D17
D15
D14
V
D12
D35
D34
D33
D29
D26
D25
D24
D23
D21
D20
D18
D13
D31
D16
D11
IW
CC
CC
CC
CC
(1)
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
31
32
33
34
35
36
37
38
25
TQFP (PK128-1, order code: PF)
TOP VIEW
TM
36-BIT FIFO
2
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
Each FIFO has a data input port (D
The input port can be selected as either a Synchronous (clocked) interface,
102
100
101
COMMERCIAL AND INDUSTRIAL
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
n
) and a data output port (Q
4667 drw02a
TEMPERATURE RANGES
OE
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
Q15
Q14
Q13
Q12
GND
Q11
Q10
V
V
V
V
V
CC
CC
CC
CC
CC
OCTOBER 22, 2008
n
), both of