IDT72V3680L10PF IDT, Integrated Device Technology Inc, IDT72V3680L10PF Datasheet - Page 3

• Manufacturer Part Number: IDT72V3680L10PF
• Description: IC FIFO SS 16384X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3680L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3680L10PF

WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.
PIN CONFIGURATIONS (CONTINUED)
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
The output port can be selected as either a Synchronous (clocked) interface,
A
B
C
D
F
H
K
L
E
G
J
M
ASYW
SEN
D32
D26
D21
D12
D10
D35
D29
D18
D15
D9
1
WEN
D34
D31
D25
D22
D19
D16
D11
D28
D13
IW
D8
2
A1 BALL PAD CORNER
WCLK
PRS
D27
D33
D30
D24
D23
D20
D14
D17
D6
D7
3
FWFT/SI
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
V
V
V
V
PAF
V
V
D4
D5
LD
4
CC
CC
CC
CC
D3
CC
CC
FF/IR
MRS
GND
GND
GND
GND
V
OW
V
D0
D1
D2
5
CC
CC
TRST
GND
GND
GND
GND
GND
GND
FS0
V
TMS
V
HF
CC
CC
6
TOP VIEW
TM
3
36-BIT FIFO
to f
of the one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
GND
GND
GND
GND
GND
GND
V
TCK
V
FS1
MAX
BM
TDI
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
In FWFT mode, the first word written to an empty FIFO is clocked directly
There are two possible timing modes of operation with these devices: IDT
CC
CC
7
with complete independence. There are no restrictions on the frequency
ASYR
GND
GND
GND
GND
V
TDO
V
Q0
BE
Q1
EF
CC
8
CC
RCLK
PAE
V
V
V
V
V
V
Q2
Q3
Q4
IP
CC
CC
CC
CC
CC
9
CC
PFM
Q29
Q16
REN
RM
Q26
Q23
Q19
Q13
Q22
Q5
Q6
10
COMMERCIAL AND INDUSTRIAL
Q15
Q10
Q32
Q30
Q18
Q24
Q21
Q12
Q27
Q7
OE
11
RT
TEMPERATURE RANGES
4667 drw02b
Q20
Q17
OCTOBER 22, 2008
Q35
Q34
Q31
Q25
Q14
Q11
Q28
Q8
Q3
Q9
3
12