IDT72V3680L10PF IDT, Integrated Device Technology Inc, IDT72V3680L10PF Datasheet - Page 40

• Manufacturer Part Number: IDT72V3680L10PF
• Description: IC FIFO SS 16384X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3680L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3680L10PF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
Figure 29. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72 and 32,768 x 72 Width Expansion
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
D
0
- Dm
LOAD (LD)
m
#1
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
FIFO
IDT
#1
Dm
m
+1
- Dn
TM
Q
40
0
36-BIT FIFO
n
- Qm
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
72V3650/72V3660/72V3670/72V3680/72V3690 devices. D
device form a 72-bit wide input bus and Q
bit wide output bus. Any word width can be attained by adding additional
IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 devices.
Figure 29 demonstrates a width expansion using two IDT72V3640/
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
FIFO
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Qm
+1
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
0
-Q
TEMPERATURE RANGES
35
from each device form a 72-
DATA OUT
OCTOBER 22, 2008
4667 drw34
0
- D
35
from each
GATE
(1)