IDT72V3680L10PF IDT, Integrated Device Technology Inc, IDT72V3680L10PF Datasheet - Page 34

• Manufacturer Part Number: IDT72V3680L10PF
• Description: IC FIFO SS 16384X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3680L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3680L10PF

NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
D
Q
WCLK
RCLK
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
WCLK
RCLK
WEN
REN
0
0
PAF
WEN
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768
for the IDT72V3690.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the
IDT72V3690.
rising edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW2
- D
- Q
LD
LD
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKL
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
DATA IN OUTPUT REGISTER
t
ENH
t
CLKH
t
CLKH
1
(2)
t
CLK
t
CLK
SKEW2
t
t
ENS
LDS
t
t
CLKL
DS
t
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
TM
t
PAFS
34
36-BIT FIFO
t
t
t
ENH
DH
LDH
t
LDH
t
t
t
ENH
A
ENS
t
SKEW2
(3)
OFFSET
PAF
PAE OFFSET
t
ENH
D - m words in FIFO
t
1
t
t
DH
LDH
ENH
t
t
ENH
LDH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
TEMPERATURE RANGES
2
PAFS
t
PAFS
OCTOBER 22, 2008
PAF OFFSET
). If the time between the
D-(m+1) words
in FIFO
4667 drw23
4667 drw21
4667 drw22
(2)