IDT72V3680L10PF IDT, Integrated Device Technology Inc, IDT72V3680L10PF Datasheet - Page 44

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IDT72V3680L10PF

Manufacturer Part Number
IDT72V3680L10PF
Description
IC FIFO SS 16384X36 10NS 128TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3680L10PF

Function
Asynchronous, Synchronous
Memory Size
576K (16K x 36)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3680L10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V3680L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V3680L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
1149.1) for the full state diagram
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
CAPTURE-DR
Register.
SHIFT-DR
of TCLK in the TDI/TDO path and shifted out serially, LSB first at the falling edge
of TCLK towards the output.
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
All state transitions within the TAP controller occur at the rising edge of the
Data is loaded from the parallel input pins or core outputs into the Data
The previously captured data is shifted in serially, LSB first at the rising edge
Input = TMS
1
0
Test-Logic
Run-Test/
Reset
Idle
0
Figure 33. TAP Controller State Diagram
1
1
0
1
Update-DR
Capture-DR
Pause-DR
Exit2-DR
DR-Scan
Shift-DR
EXit1-DR
Select-
TM
44
0
36-BIT FIFO
0
0
1
1
1
0
UPDATE-DR
parallel outputs in this state to be accessed through the internal bus.
EXIT1-DR / EXIT2-DR
to TCK while in this state causes the controller to enter the Update-DR state. This
terminates the scanning process. All test data registers selected by the current
instruction retain their previous state unchanged.
PAUSE-DR
between TDI and TDO to be temporarily halted. All test data registers selected
by the current instruction retain their previous state unchanged.
similar to Data registers. These instructions operate on the instruction registers.
0
0
The shifting process has been completed. The data is latched into their
This is a temporary controller state. If TMS is held high, a rising edge applied
This controller state allows shifting of the test data register in the serial path
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
1
1
0
1
1
1
1
1
Capture-IR
Update-IR
Pause-IR
Exit2-IR
IR-Scan
Exit1-IR
Shift-IR
Select-
1
0
0
0
0
COMMERCIAL AND INDUSTRIAL
4667 drw38
0
0
1
TEMPERATURE RANGES
OCTOBER 22, 2008

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