IDT72V3680L10PF IDT, Integrated Device Technology Inc, IDT72V3680L10PF Datasheet - Page 6

• Manufacturer Part Number: IDT72V3680L10PF
• Description: IC FIFO SS 16384X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3680L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3680L10PF

NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION (TQFP AND PBGA PACKAGES)
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
BM
BE
D
EF/OR
FF/IR
FSEL0
FSEL1
FWFT/SI
HF
IP
IW
LD
OE
OW
MRS
PAE
PAF
PFM
PRS
Q
RCLK/
REN
RM
RT
RD
Symbol
0
0
(1)
–D
(1)
–Q
(1)
(1)
(1)
(1)
(1)
35
35
(1)
(1)
Bus-Matching
Big-Endian/
Little-Endian
Data Inputs
Empty Flag/
Output Ready
Full Flag/
Flag Select Bit 0
Flag Select Bit 1
First Word Fall
Through/Serial In
Half-Full Flag
Interspersed Parity I
Input Width
Load
Output Enable
Output Width
Master Reset
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Programmable
Flag Mode
Partial Reset
Data Outputs
Read Clock/
Read Strobe
Read Enable
Retransmit Timing
Mode
Retransmit
Input Ready
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
as a serial input for loading offset registers.
will select Synchronous Programmable flag timing mode.
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will
select Little-Endian format.
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the
FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO
memory.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable
flags PAE and PAF. There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable
flags PAE and PAF. There are up to eight possible settings available.
HF indicates whether the FIFO memory is more or less than half-full.
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not
effect the data written to and read from the FIFO.
This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight progammable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency
timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all
retained.
Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operation of the RCLK/RD input is only available in the PBGA package.
REN enables RCLK for reading data from the FIFO memory and offset registers.
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
OE controls the output impedance of Q
one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
state. Outputs are not 5V tolerant regardless of the state of OE.
This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines
TM
36-BIT FIFO
6
n.
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008