LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 224

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Analog-to-Digital Converter (ADC)
224
Reset
Reset
Type
Type
ADC Sample Sequence Control 3 (ADCSSCTL3)
Offset 0x0A4
RO
RO
31
15
0
0
Register 23: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x064
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. This register’s bit
fields are as shown in the diagram below. Bit field definitions are the same as those in the
ADCSSCTL0 register (see page 215) but are for Sample Sequencer 3.
Register 24: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8
This register contains the conversion results for samples collected with Sample Sequencer 3.
Reads of this register return the conversion result data. If the FIFO is not properly handled by
software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT
registers.
Bit fields and definitions are the same as ADCSSFIFO0 (see page 217) but are for FIFO 3.
Register 25: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC
This register provides a window into the Sample Sequencer FIFO 3, providing full/empty status
information as well as the positions of the head and tail pointers. The reset value of 0x100
indicates an empty FIFO.
This register has the same bit fields and definitions as ADCSSFSTAT0 (see page 218) but is for
FIFO 3.
RO
RO
30
14
0
0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TS0
R/W
RO
19
0
3
0
R/W
IE0
RO
18
0
2
0
END0
R/W
RO
July 5, 2006
17
0
1
1
R/W
D0
RO
16
0
0
0