LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 80

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
80
Bit/Field
26:23
19:17
22
21
20
USEPWMDIV
USESYSDIV
PWMDIV
reserved
SYSDIV
Name
Type
R/W
R/W
R/W
R/W
RO
Reset
0xF
0x7
0
0
0
Preliminary
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock
from the PLL output (200 MHz).
When reading the Run-Mode Clock Configuration (RCC)
register (see page 79), the SYSDIV value is MINSYSDIV if
a lower divider was requested and the PLL is being used.
This lower value is allowed to divide a non-PLL source.
clock. The system clock divider is forced to be used when
the PLL is selected as the source.
Reserved bits return an indeterminate value, and should
never be changed.
Use the PWM clock divider as the source for the PWM
clock.
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the
system clock down for use as the timing reference for the
PWM module. This clock is only power 2 divide and rising
edge is synchronous without phase shift from PCLK/HCLK.
Use the system clock divider as the source for the system
Value
000
001
010
100
101
Binary
011
110
111
Value
0000-
1000
1001
1010
1011
1100
1101
1110
1111
Divisor
(BYPASS=1)
reserved
/10
/11
/12
/13
/14
/15
/16
Divisor
/2
/4
/8
/16
/32
/64
/64
/64 (default)
Frequency
(BYPASS=0)
reserved
20 MHz
18.18 MHz
16.67 MHz
15.38 MHz
14.29 MHz
13.33 MHz
12.5 MHz (default)
July 5, 2006