LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 26

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Architectural Overview
1.4
1.4.1
1.4.1.1
1.4.1.2
1.4.2
1.4.2.1
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Functional Overview
The following sections provide an overview of the features of the LM3S301 microcontroller. The
chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and
support information can be found in “Ordering and Contact Information” on page 365.
ARM Cortex™-M3
Processor Core (Section 2 on page 32)
All members of the Stellaris product family, including the LM3S301 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core
for a high-performance, low-cost platform that meets the needs of minimal memory
implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
Section 2, “ARM Cortex-M3 Processor Core,” on page 32 provides an overview of the ARM core;
the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.
Nested Vectored Interrupt Controller (NVIC)
The LM3S301 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. Software can set eight priority levels on 7
exceptions (system handlers) and 22 interrupts.
Section 4, “Interrupts,” on page 37 provides an overview of the NVIC controller and the interrupt
map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference
Manual.
Motor Control Peripherals
To enhance motor control, the LM3S301 controller features Pulse Width Modulation (PWM)
outputs.
PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power
supplies and motor control.
On the LM3S301, PWM motion control functionality can be achieved through dedicated, flexible
motion control hardware (the PWM pins) or through the motion control features of the
general-purpose timers (using the CCP pins).
PWM Pins (Section 15 on page 309)
The LM3S301 PWM module consists of one PWM generator block and a control block. Each PWM
generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM
signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block
determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
Preliminary
July 5, 2006