LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 66

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
66
Reset
Reset
Type
Type
23:19
Bit/Field
Device Capabilities 3 (DC3)
Offset 0x018
25
18
17
16
11
31:27
15:12
RO
RO
31
15
0
0
5:2
26
24
10
9
8
7
6
Register 6: Device Capabilities 3 (DC3), offset 0x018
Note:
This register is predefined by the part and can be used to verify features.
RO
RO
30
14
0
0
reserved
reserved
reserved
reserved
reserved
reserved
Name
CCP2
CCP0
ADC2
ADC1
ADC0
reserved
C1o
C1+
C0o
C0+
C1-
C0-
RO
RO
The bit diagram indicates all possible features. The table below indicates values for your
specific part.
29
13
0
0
RO
RO
28
12
0
0
Type
C1o
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
1
CCP2
C1+
RO
RO
26
10
1
1
reserved
Reset
C1-
RO
RO
25
0
9
1
0
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
Preliminary
CCP0
C0o
RO
RO
24
1
8
1
Description
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the Capture/
Compare/PWM pin 2.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the Capture/
Compare/PWM pin 0.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the ADC2 pin.
A 1 in this bit indicates the presence of the ADC1 pin.
A 1 in this bit indicates the presence of the ADC0 pin.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the C1o pin.
A 1 in this bit indicates the presence of the C1+ pin.
A 1 in this bit indicates the presence of the C1- pin.
A 1 in this bit indicates the presence of the C0o pin.
A 1 in this bit indicates the presence of the C0+ pin.
A 1 in this bit indicates the presence of the C0- pin.
Reserved bits return an indeterminate value, and should
never be changed.
C0+
RO
RO
23
0
7
1
C0-
RO
RO
22
0
6
1
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
reserved
RO
RO
19
0
3
0
ADC2
RO
RO
18
1
2
0
PWM1
ADC1
RO
RO
17
July 5, 2006
1
1
1
PWM0
ADC0
RO
RO
16
1
0
1