LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 246

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Universal Asynchronous Receiver/Transmitter (UART)
246
Reset
Reset
Type
Type
UART Interrupt Mask (UARTIM)
Offset 0x038
31:11
RO
RO
31
15
0
0
Bit
10
9
8
7
6
Register 9: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
RO
RO
30
14
0
0
reserved
Name
OEIM
BEIM
PEIM
FEIM
RTIM
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
OEIM
R/W
RO
26
10
0
0
Reset
0
0
0
0
0
0
BEIM
R/W
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt
controller.
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt
controller.
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt
controller.
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt
controller.
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt
controller.
PEIM
R/W
RO
24
0
8
0
reserved
FEIM
R/W
RO
23
0
7
0
RTIM
R/W
RO
22
0
6
0
TXIM
R/W
RO
21
0
5
0
RXIM
R/W
RO
20
0
4
0
RO
19
RO
0
3
0
RO
18
RO
0
2
reserved
0
RO
17
RO
July 5, 2006
0
1
0
RO
16
RO
0
0
0