LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 81

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 5, 2006
Oscillator-Related Bits
Bit/Field
16:14
9:6
5:4
13
12
10
11
OSCSRC
reserved
BYPASS
PWRDN
PLLVER
Name
XTAL
OEN
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
Reset
0xB
0x0
0
1
1
1
0
Preliminary
Description
Reserved bits return an indeterminate value, and should
never be changed.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. See Table 6-4 on page 82 for
PLL mode control.
PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwise, the PLL clock does not oscillate outside the PLL
module.
Note:
PLL Bypass
Chooses whether the system clock is derived from the PLL
output or the OSC source. If set, the clock that drives the
system is the OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
Note:
PLL Verification
This bit controls the PLL verification timer function. If set,
the verification timer is enabled and an interrupt is
generated if the PLL becomes inoperative. Otherwise, the
verification timer is not enabled.
This field specifies the crystal value attached to the main
oscillator. The encoding for this field is provided in Table 6-4
on page 82.
Picks among the four input sources for the OSC. The
values are:
Value
00
01
10
11
Both PWRDN and OEN must be cleared to run the
PLL.
The ADC module cannot be used when the PLL is
in Bypass mode (BYPASS set to 1).
Input Source
Main oscillator (default)
Internal oscillator
Internal oscillator / 4 (this is necessary if used
as input to PLL)
reserved
LM3S301 Data Sheet
81