SPFD54124B Drise, SPFD54124B Datasheet - Page 11

• Manufacturer Part Number: SPFD54124B
• Description: 396-Channel 6-Bit Source Driver
• Manufacturer: Drise

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Interface input Signals
CSX
D/CX
(SCL)
WRX
(R/WX)
RDX
(E)
SDA
DB0-DB17
VS
HS
DE
PCLK
OSC
Charge Pump and Power Supply Signal
Signal
Pin No.
1
1
1
1
1
1
1
1
1
1
1
I/O
I
I
I
I
I/O
I/O
I
I
I
I
O
Connected with
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
Function
Chip select signal.
Low: the SPFD54124B is accessible
High: the SPFD54124B is not accessible
This pin has can be permanently fixed “Low” in MCU interface mode only.
Display data / Command selection pin in parallel interface
Low: Command data
High: Display data
In SPI I/F, this is used as SCL pin.
Must connect to the GND or VDDIO level when not used.
(A) In 80-system interface mode, a write strobe signal can be input via this pin
(B) In 68-system interface mode, a write or read control signal can be input via
this pin and initializes a write or read operation.
Must connect to the GND or VDDIO level when not used.
In 80-system interface mode, a read strobe signal can be input via this pin and
initializes a read operation when the signal is low.
In 68system interface mode, a strobe signal can be input via this pin and
initializes a write or read operation when the signal is low.
Must connect to the GND or VDDIO level when not in use.
(A) When RCM = ‘1’ (RGB I/F),
(B) When RCM = ‘0’ (MCU I/F),
If not used, please fix this pin at VDDIO or DGND level.
(A) When RCM = ‘1’ (RGB I/F),
(B) When RCM = ‘0’ (MCU I/F),
In SPI I/F, D[17:1] not used, please fix this pin at VDDIO or DGND level.
In external interface mode, served as a vertical synchronize signal input
Must connect to the VDDIO or DGND level when not in use.
In external interface mode, served as a horizontal synchronized signal input
Must connect to the VDDIO or DGND level when not in use.
In external interface mode, polarity of DE signal is synchronized with valid
graphic data input.
High: Valid data on DB17-DB0
Low: Invalid data on DB17-DB0
Must connect to the VDDIO or DGND level when not in use.
In external interface mode, served as a dot clock signal.
Must connect to the VDDIO or DGND level when not in use.
Oscillator frequency output pin for oscillator testing and turn ON/OFF by S/W
command.
(C) In SPI I/F, D0 is used as Serial input/ output signal.
Serial input/ output signal in serial I/F mode.
The data is input on the rising edge of the SCL signal.
The data is output on the falling edge of the SCL signal.
This pin is not used, and fix at VDDIO or DGND level.
D[17:0] are used for RGB interface data bus
D[17:0] are used to MCU parallel interface data bus
and initializes a write operation when the signal is low.
11
SPFD54124B
Preliminary
Preliminary Version: 0.6
APR. 26, 2007