SPFD54124B Drise, SPFD54124B Datasheet - Page 142

• Manufacturer Part Number: SPFD54124B
• Description: 396-Channel 6-Bit Source Driver
• Manufacturer: Drise

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7.4. RGB interface
7.4.1.
The module uses 6, 16 and 18-bits parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after
Power On sequence.
Pixel clock (PCLK) is running all the time without stoping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising
edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In –mode etc.
Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (‘0’, low) active and its state
is read to the display module by a rising edge of he PCLK signal.
Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (‘0’, low) active and its state
is read to the display module by a rising edge of the PCLK signal.
Data Enable (DE) is used to tell when there is received a RGB information that should be transferred on the display. This is a positive (‘1’,
high) active and its state is read to the display module by a rising edge of the PCLK signal.
D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is
transferred on the display (When DE=’1’ and there is a rising edge of PCLK). D[17:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a
rising edge of the PCLK signal.
The PCLK cycle is described in the following figure.
Note: PCLK is an unsynchronized signal (It can be stopped).
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General Description
VS, HS, DE
D[17:0]
PCLK
The host changes D[17:0], VS,
HS and DE lines when there is a
falling edge of the PCLK
Fig. 7.4.1 PCLK cycle
The driver read the D[17:0], VS,
HS and DE lines when there is a
falling edge of the PCLK
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SPFD54124B
Preliminary
Preliminary Version: 0.6
APR. 26, 2007