SPFD54124B Drise, SPFD54124B Datasheet - Page 187

• Manufacturer Part Number: SPFD54124B
• Description: 396-Channel 6-Bit Source Driver
• Manufacturer: Drise

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7.9. Preset Values
ORISETECH has already set all preset values in SPFD54124B. Any of these preset values do not need customer’s SW support.
7.10. Power ON/OFF Sequence
VDDIO and VDD can be applied in any order.
VDDIO and VDD can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VDD and VDDIO must be powered down minimum 120msec after RESX has been
released.
During power off, if LCD is in the Sleep In mode, VDDIO or VDD can be powered down minimum 0msec after RESX has been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out
If RESX line is not held stable by host during Power On Sequence, then it will be necessary to apply a Hardware Reset (RESX) after Host
Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed.
The power on/off sequence is illustrated below:
7.10.1. Case 1 – RESX Line is held High or Unstable by Host at Power On
If RESX line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD and VDDIO
have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
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Proprietary & Confidential
command. Also between receiving Sleep In command and Power Off Sequence.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
RESX
VDD1
VDD2
VDDIO
VDD
CSX
RESX
!RES
!RES
!CS
Sleep Out mode)
(Power down in
(Power down in
Sleep In mode)
H or L
Tr
PW =
Time when the latter signal rises up to 90% of its Typical Value.
e.g. When VDD2 comes later, This time is defined at the cross point
of 90% of 2.5V/2.75V, not 90% of 2.3V.
Time when the former signal falls down to 90% of its Typical Value.
e.g. When VDD2 falls earlier, This time is defined at the cross point
of 90% of 2.5V/2.75V, not 90% of 2.3V.
TfpwRESX1
TfpwRESX2
30%
30%
+/- no limit
tf
tf
PW!RES1
PW!RES2
tr
2.75V,not 90% of
2.75V,not 90% of
PW!CS
CSX
tr
tr
is applied to !RES falling in the Sleep Out Mode.
is applied to !RES falling in the Sleep In Mode.
PW!RES
PW!RES
= +/- no limit
RESX
RES
tf
PW!RES1
= + no limit
= + no limit
RESX1
RESX
RESX
tf
187
= min.120ms
PW!CS
CSX
= +/- no limit
tf
tf
PW!RES2
PW =
RESX2
+/- no limit
= min.0ns
SPFD54124B
Preliminary
Preliminary Version: 0.6
APR. 26, 2007