spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 36

• Manufacturer Part Number: spd6722qcce
• Description: Isa-to-pc-card Pcmcia Controllers
• Manufacturer: Intel Corporation

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
4.1.12
4.1.12.1
4.1.13
4.1.14
4.2
36
Programmable PC Card Timing
The Setup, Command, and Recovery time for the PC Card bus is programmable (see
Registers” on page
PC Card. There are two sets of timing registers, Timer Set 0 and Timer Set 1, that can be selected
on a per-window basis for both I/O and memory windows.
To be compatible with the 82365SL, the two timing sets are programmed at the rising edge of
PWRGOOD to include normal-wait and one-wait-state timing.
ATA Mode Operation
The PD67XX supports direct connection to AT-attached-interface hard drives. ATA drives use an
interface very similar to the IDE interface found on many popular portable computers. In this
mode, the address and data conflict with the floppy drive is handled automatically. See
Operation” on page 88
DMA Mode Operation for the PD6722
A slave mode Direct Memory Access (DMA) feature exists in the PD6722. To use DMA mode, the
Interrupt and General Control register, bit 5 must be set to ‘1’ to operate the PC Card in I/O
Card Interface mode. PC Card interface DMA handshake signal options must also be selected.
Refer to the description of the
page 78
Selective Data Drive for I/O Windows
The PD67XX can be programmed to drive only some of the ISA bus data pins on reads from I/O
windows. This reduces data contention for I/O addresses that include more than one peripheral. In
the standard IBM PC AT, I/O map, floppy disk, and hard disk share address 3F7h. The floppy
disk drives ISA-data-bus bit 7 on a read from 3F7h, and the hard disk drives bits 6:0. To allow both
floppy disk controllers on the motherboard and hard disks on the PC Card bus (or vice versa) to
coexist, the PD67XX can be programmed through use of its Data Mask registers to disable bit 7 on
I/O reads at addresses 3F7h and 377h. This is done by programming up I/O windows to these
addresses as part of the task of configuring a socket for ATA drive support (see
page
Host Access to Registers
The PD67XX registers are accessed through an 8-bit indexing mechanism. An index register
scheme allows a large number of internal registers to be accessed by the CPU using only two I/O
addresses.
•
byte lane on which the transfer is to occur. The data is transferred to/from the data bus (see
Table
8-Bit Transfer from 8-Bit Processor — The CPU puts the address on the bus. The host
determines that it will be an 8-bit transfer since the SBHE* signal has been tied high. The
PD67XX queries SA0 to determine if the byte is odd/even. The data is transferred to/from the
Data bus (D[7:0]).
77). Alternately, all bits except bit 7 can also be disabled to allow the opposite case.
as well as
9).
“DMA Operation (PD6722 only)” on page
84). The PD67XX can be programmed to match the timing requirements of any
for more information.
“Extension Control 1 (PD6722 only, formerly DMA Control)” on
97.
“Extended Data” on
“Timing
“ATA Mode
Datasheet