spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 93

• Manufacturer Part Number: spd6722qcce
• Description: Isa-to-pc-card Pcmcia Controllers
• Manufacturer: Intel Corporation

13.2
Datasheet
PWRGOOD
Figure 13. Example GPSTB Write Port (Extension Control 2 bits 4:3 are ‘10’)
Figure 14. Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘01’)
SD[15:0]
SD[15:0]
(16-bit bus)
(16-bit bus)
IOW*
IOR*
Example Implementations of GPSTB-Controlled Read and
Write Ports
In this mode, Extension Control 2 register bit 4 is set to ‘1’ enabling the GPSTB pin to function as
a write strobe. Writes to the respective extended index 0Ah cause the respective GPSTB to go
active (low) for the duration of the system’s IOW* pulse.
On writes, data is written to both the external latch and the internal shadow copy of the External
Data register. A read of the respective extended index 0Ah would produce the last value written to
the latch.
Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes
all ‘0’s at its outputs when the PD67XX is reset.
IOW*
SD[15:0]
IOR*
SD[15:0]
PD6722
PD6722
GPSTB
GPSTB
†
Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
†
Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
EXT_WR*
EXT_RD*
Pull-up
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
†
Pull-up
General-
Purpose
SD[15:8]
Inputs
†
(for example, ’374)
(for example, ’244)
Tristate Buffer
RES
CK
D
OE
D7
D0
Latch
O7
O0
O
SD[15:8]
General-
Purpose
Outputs
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