spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 59

• Manufacturer Part Number: spd6722qcce
• Description: Isa-to-pc-card Pcmcia Controllers
• Manufacturer: Intel Corporation

8.2
Datasheet
Register Name: System I/O Map 0–1 Start Address Low
Index: 08h, 0Ch
Bit 7
Bit 4 — I/O Window 1 Size
When bit 5 below is ‘0’, this bit determines the size of the data path to I/O Window 1. When bit 5 is
‘1’, this bit is ignored.
Bit 5 — Auto-Size I/O Window 1
This bit determines the width of the data path to I/O Window 1. Note that when this bit is ‘1’, the
-IOIS16 signal (see
proper ATA mode operation (see
Bit 7 — Timing Register Select 1
This bit determines the access timing specification for I/O Window 1 (see
page
System I/O Map 0–1 Start Address Low
There are two separate System I/O Map Start Address Low registers, each with identical fields.
These registers are located at the following indexes:
Bit 6
84).
0
1
0
1
0
1
Index
8h
Ch
8-bit data path to I/O Window 1.
16-bit data path to I/O Window 1.
I/O Window 1 Size (see bit 4) determines the data path to I/O Window 1.
The data path to I/O Window 1 will be determined based on -IOIS16 returned by the card.
Accesses made with timing specified in Timing Set 0.
Accesses made with timing specified in Timing Set 1.
Bit 5
System I/O Map Start Address Low
System I/O Map 0 Start Address Low
System I/O Map 1 Start Address Low
Table 2 on page
Bit 4
“ATA Mode Operation” on page
Start Address 7:0
RW:00000000
20) determines the window size. This bit must be set for
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 3
Bit 2
88).
Register Compatibility Type: 365
“Setup Timing 0–1” on
Bit 1
Register Per: socket
Bit 0
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