rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 11

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

2001-11-9
00A4h–00ABh
00ACh–00B3h
00B4h–00BBh
00BCh–00C3h
00C4h–00CBh
009Ch–00A3h
005Ch-005Dh
006Ah-006Bh
006Ch-006Dh
008Ch–0093h
0094h–009Bh
007Ch-007Fh
006Eh-006Fh
0078h-007Bh
0054h-0057h
0060h-0061h
0062h-0063h
0064h-0065h
0066h-0067h
0068h-0069h
0070h-0071h
0072h-0073h
0074h-0075h
0076-0077h
0081-0083h
00CCh
00CDh
0053H
005Ah
008Ah
00CEh
00CFh
00D0h
00D1h
005Bh
005Eh
008Bh
0052h
0058h
0059h
005Fh
0080h
0084h
0085h
0086h
0087h
0088h
0089h
R /W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
-
-
-
-
-
PHY1_PARM
PHY2_PARM
TW_PARM
NWAYTR
LSBCRC0
LSBCRC1
LSBCRC2
LSBCRC3
LSBCRC4
LSBCRC5
CONFIG1
CONFIG3
CONFIG4
ANLPAR
MULINT
Wakeup0
Wakeup1
Wakeup2
Wakeup3
Wakeup4
Wakeup5
Wakeup6
Wakeup7
TimerInt
RERID
BMCR
ANAR
BMSR
ANER
TSAD
CSCR
CRC5
CRC6
CRC7
FCSC
CRC0
CRC1
CRC2
CRC3
CRC4
MSR
REC
DIS
-
-
-
-
-
Configuration Register 1
Reserved
Timer Interrupt Register: Once having written a nonzero value to
this register, the Timeout bit of the ISR register will be set whenever
the TCTR reaches to this value. The Timeout bit will never be set as
long as the TimerInt register is zero.
Media Status Register
Configuration register 3
Configuration register 4
Reserved
Multiple Interrupt Select
PCI Revision ID = 10h.
Reserved
Transmit Status of All Descriptors
Basic Mode Control Register
Basic Mode Status Register
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Register
Auto-Negotiation Expansion Register
Disconnect Counter
False Carrier Sense Counter
N-way Test Register
RX_ER Counter
CS Configuration Register
Reserved
PHY parameter 1
Twister parameter
PHY parameter 2
Reserved
Power Management CRC register0 for wakeup frame0
Power Management CRC register1 for wakeup frame1
Power Management CRC register2 for wakeup frame2
Power Management CRC register3 for wakeup frame3
Power Management CRC register4 for wakeup frame4
Power Management CRC register5 for wakeup frame5
Power Management CRC register6 for wakeup frame6
Power Management CRC register7 for wakeup frame7
Power Management wakeup frame0 (64bit)
Power Management wakeup frame1 (64bit)
Power Management wakeup frame2 (64bit)
Power Management wakeup frame3 (64bit)
Power Management wakeup frame4 (64bit)
Power Management wakeup frame5 (64bit)
Power Management wakeup frame6 (64bit)
Power Management wakeup frame7 (64bit)
LSB of the mask byte of wakeup frame0 within offset 12 to 75
LSB of the mask byte of wakeup frame1 within offset 12 to 75
LSB of the mask byte of wakeup frame2 within offset 12 to 75
LSB of the mask byte of wakeup frame3 within offset 12 to 75
LSB of the mask byte of wakeup frame4 within offset 12 to 75
LSB of the mask byte of wakeup frame5 within offset 12 to 75
11
RTL8100B(L)
Rev.1.41