rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 17

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

5.8 Receive Configuration Register
(Offset 0044h-0047h, R/W)
This register is used to set the receive configuration for the RTL8100B(L). Receive properties such as accepting error packets,
runt packets, setting the receive drain threshold etc. are controlled here.
2001-11-9
31-28
27-24
23-18
7-4
3-1
Bit
17
16
0
R/W
R/W
R/W
R/W
R/W
W
-
-
-
ERTH3, 2, 1, 0
MulERINT
CLRABT
Symbol
TXRR
RER8
-
-
-
Tx Retry Count: These are used to specify additional transmission
retries in multiple of 16 (IEEE 802.3 CSMA/CD retry count). If the
TXRR is set to 0, the transmitter will re-transmit 16 times before
aborting due to excessive collisions. If the TXRR is set to a value
greater than 0, the transmitter will re-transmit a number of times equals
to the following formula before aborting:
The TER bit in the ISR register or transmit descriptor will be set when
the transmission fails and reaches to this specified retry count.
Reserved
Clear Abort: Setting this bit to 1 causes the RTL8100B(L) to
retransmit the packet at the last transmitted descriptor when this
transmission was aborted, Setting this bit is only permitted in the
transmit abort state.
Reserved
Early Rx threshold bits: These bits are used to select the Rx threshold
multiplier of the whole packet that has been transferred to the system
buffer in early mode when the frame protocol is under the
RTL8100B(L)'s definition.
0000 = no early Rx threshold
0010 = 2/16
0100 = 4/16
0110 = 6/16
1000 = 8/16
1010 = 10/16
1100 = 12/16
1110 = 14/16
Reserved
Multiple early interrupt select: When this bit is set, any received
packet invokes early interrupt according to MULINT<MISR[11:0]>
setting in early mode. When this bit is reset, the packets of familiar
protocols (IPX, IP, NDIS, etc) invoke early interrupt according to
RCR<ERTH[3:0]> setting in early mode. The packets of unfamiliar
protocols will invoke early interrupt according to the setting of
MULINT<MISR[11:0]>.
The RTL8100B(L) receives the error packet whose length is larger than
8 bytes after setting the RER8 bit to 1.
when the RER8 bit is cleared. The power-on default is zero.
receives an error packet whose length is larger than 8 bytes. The RER8
is “ Don’t care “ in this situation.
The RTL8100B(L) receives the error packet larger than 64-byte long
If AER or AR is set, the RER will be set when the RTL8100B(L)
17
Total retries = 16 + (TXRR * 16)
Description
0001 = 1/16
0011 = 3/16
0101 = 5/16
0111 = 7/16
1001 = 9/16
1011 = 11/16
1101 = 13/16
1111 = 15/16
RTL8100B(L)
Rev.1.41