rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 38

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register
RID: Revision ID Register
PIFR: Programming Interface Register
SCR: Sub-Class Register
BCR: Base-Class Register
CLS: Cache Line Size
LTR: Latency Timer Register
HTR: Header Type Register
2001-11-9
10-9
Bit
0-3
15
14
13
12
11
8
7
6
5
4
The Revision ID register is an 8-bit register that specifies the RTL8100B(L) controller revision number.
The programming interface register is an 8-bit register that identifies the programming interface of the RTL8100B(L)
controller. Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h.
The Sub-class register is an 8-bit register that identifies the function of the RTL8100B(L). SCR = 00h indicates that the
RTL8100B(L) is an Ethernet controller.
The Base-class register is an 8-bit register that broadly classifies the function of the RTL8100B(L). BCR = 02h indicates
that the RTL8100B(L) is a network controller.
Reads will return a 0, writes are ignored.
Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8100B(L).
When the RTL8100B(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8100B(L) deasserts FRAMEB
prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8100B(L)
initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is
00H.
Reads will return a 0, writes are ignored.
behave normally. Writes are slightly different in that bits can be reset, but not set.
RMABT
NewCap
Symbol
DPERR
RTABT
DST1-0
STABT
SSERR
66MHz
FBBC
DPD
UDF
-
Detected Parity Error: When set indicates that the RTL8100B(L) detected a parity error, even if parity
error handling is disabled in command register PERRSP bit.
Signaled System Error: When set indicates that the RTL8100B(L) asserted the system error pin,
SERRB. Writing a 1 clears this bit to 0.
Received Master Abort: When set indicates that the RTL8100B(L) terminated a master transaction
with master abort. Writing a 1 clears this bit to 0.
Received Target Abort: When set indicates that the RTL8100B(L) master transaction was terminated
due to a target abort. Writing a 1 clears this bit to 0.
Signaled Target Abort: Set to 1 whenever the RTL8100B(L) terminates a transaction with target abort.
Writing a 1 clears this bit to 0.
Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),
indicating the RTL8100B(L) will assert DEVSELB two clocks after FRAMEB is asserted.
Data Parity error Detected:
This bit sets when the following conditions are met:
☼ The RTL8100B(L) asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by another
device.
☼ The RTL8100B(L) operates as a bus master for the operation that caused the error.
☼ The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operation has no effect.
Config3<FbtBEn>=1, Read as 1.
User Definable Features Supported: Read as 0, write operation has no effect. The RTL8100B(L) does
not support UDF.
66 MHz Capable: Read as 0, write operation has no effect. The RTL8100B(L) has no 66MHz
capability.
New Capability: Config3<PMEn>=0, Read as 0, write operation has no effect. Config3<PMEn>=1, Read as
1.
Reserved
38
Description
RTL8100B(L)
Rev.1.41