rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 22

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

5.13 CONFIG 3: Configuration Register3
(Offset 0059h, R/W)
2001-11-9
Bit
3-1
7
6
5
4
0
R/W
R/W
R/W
R/W
R
R
-
PARM_En
GNTSel
Symbol
FBtBEn
LinkUp
Magic
-
Reserved
Gnt Select: Select the Frame’s asserted time after the Grant signal has
been asserted. The Frame and Grant are the PCI signals.
Parameter Enable: (Used in 100Mbps mode only)
PHY1_PARM, PHY2_PARM, and TW_PARM registers to be written via
software.
and disable writing to the PHY1_PARM, PHY2_PARM and
TW_PARM registers via software.
Magic Packet: This bit is valid when the PWEn bit of the CONFIG1
register is set. The RTL8100B(L) will assert the PMEB signal to
wakeup the operating system when the Magic Packet is received.
and has been put into adequate state, it scans all incoming packets
addressed to the node for a specific data sequence, which indicates to
the controller that this is a Magic Packet frame. A Magic Packet frame
must also meet the basic requirements of:
multicast address, which includes the broadcast address.
with no breaks or interrupts. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream, 6
bytes of FFh. The device will also accept a multicast address, as long as
the 16 duplications of the IEEE address match the address of the ID
registers.
format is similar to the following:
Fast Back to Back Enable: Set to 1 to enable Fast Back to Back.
This set to 0 and the 9346CR register EEM1=EEM0=1 will enable the
EEPROM in this mode. The parameter auto-load process is executed
every time the Link is OK in 100Mbps mode.
MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 +
11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66
+ 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC
Link Up: This bit is valid when the PWEn bit of CONFIG1 register is
set. The RTL8100B(L), in adequate power state, will assert the PMEB
signal to wakeup the operating system when the cable connection is
re-established.
This set to 1 will allow parameters to be auto-loaded from the 93C46
Once the RTL8100B(L) has been enabled for Magic Packet wakeup
The destination address may be the node ID of the receiving station or a
The specific sequence consists of 16 duplications of 6 byte ID registers,
If the Node ID is 11h 22h 33h 44h 55h 66h, then the magic frame’s
The PHY1_PARM and PHY2_PARM can be auto-loaded from the
Destination address + source address + MISC + FF FF FF FF FF FF +
1: delay one clock from GNT assertion.
0: No delay
Destination address + Source address + data + CRC
22
Description
RTL8100B(L)
Rev.1.41