rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 21
rtl8100l
Manufacturer Part Number
rtl8100l
Description
Fast Ethernet Controller
Manufacturer
Realtek Semiconductor Corporation
Datasheet
1.RTL8100L.pdf
(58 pages)
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5.12 Media Status Register
(Offset 0058h, R/W)
This register allows configuration of device and PHY options, and provides PHY status information.
2001-11-9
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R
R
R
R
R
-
Aux_Status
SPEED_10
LdTXFCE
TXFCE/
Symbol
RXFCE
LINKB
TXPF
RXPF
-
Tx Flow Control Enable: The flow control is valid in full-duplex
mode only. This register’s default value comes from 93C46.
RX Flow control Enable: The flow control is enabled in full-duplex
mode only. The default value comes from 93C46.
Reserved
Aux. Power present Status:
1: The Aux. Power is present.
0: The Aux. Power is absent.
The value of this bit is fixed after each PCI reset.
Speed: Set, when current media is 10 Mbps mode. Reset, when current
media is 100 Mbps mode.
Inverse of Link status. 0 = Link OK. 1 = Link Fail.
Set, when RTL8100B(L) sends pause packet. Reset, when
RTL8100B(L) sends timer done packet.
Pause Flag: Set, when RTL8100B(L) is in backoff state because a
pause packet received. Reset, when pause state is clear.
NWAY FLY mode : NWAY with flow control capability
NWAY mode only : NWAY without flow control capability
half-duplex mode
full-duplex mode
RTL8100B(L)
ANE = 0 &
ANE = 0 &
21
ANE = 1
ANE = 1
ANE = 1
NWAY FLY mode
NWAY mode only
No NWAY
Description
Remote
-
-
TXFCE/LdTXFCE
RTL8100B(L)
invalid
R/W
R/W
R/W
R/O
Rev.1.41