rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 37

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

7.2 PCI Configuration Space Functions
The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The
functions of RTL8100B(L)'s configuration space are described below.
VID: Vendor ID. This field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID.
DID: Device ID. This field will default to a value of 8139h.
Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and
2001-11-9
15-10
Bit
9
8
7
6
5
4
3
2
1
0
VGASNOOP VGA palette SNOOP: Read as 0, write operation has no effect.
SCYCEN
FBTBEN
SERREN
ADSTEP
MEMEN
PERRSP
MWIEN
Symbol
BMEN
IOEN
respond to PCI cycles.
-
Reserved
Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The
RTL8100B(L) will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write
bit controls whether or not a master can do fast back-to-back transactions to different devices.
Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the
master is allowed to generate fast back-to-back transaction to different agents. A value of 0 means fast
back-to-back transactions are only allowed to the same agent. This bit’s state after RST# is 0.
System Error Enable: When set to 1, the RTL8100B(L) asserts the SERRB pin when it detects a
parity error on the address phase (AD<31:0> and CBEB<3:0> ).
Address/Data Stepping: Read as 0, write operation has no effect. The RTL8100B(L) never performs
address/data stepping.
Parity Error Response: When set to 1, RTL8100B(L) will assert the PERRB pin on the detection of
a data parity error when acting as the target, and will sample the PERRB pin as the master. When set to
0, any detected parity error is ignored and the RTL8100B(L) continues normal operation.
Parity checking is disabled after hardware reset (RSTB).
Memory Write and Invalidate cycle Enable: Read as 0, write operation has no effect.
Special Cycle Enable: Read as 0, write operation has no effect. The RTL8100B(L) ignores all special
cycle operation.
Bus Master Enable: When set to 1, the RTL8100B(L) is capable of acting as a bus master. When set
to 0, it is prohibited from acting as a PCI bus master.
For the normal operation, this bit must be set by the system BIOS.
Memory Space Access: When set to 1, the RTL8100B(L) responds to memory space accesses. When
set to 0, the RTL8100B(L) ignores memory space accesses.
I/O Space Access: When set to 1, the RTL8100B(L) responds to IO space access. When set to 0, the
RTL8100B(L) ignores I/O space accesses.
37
Description
RTL8100B(L)
Rev.1.41