rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 31

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

5.28 Config5: Configuration Register 5
(Offset 00D8h, R/W)
This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no need to enable Config
register write prior to writing to Config5.
2001-11-9
Bit
7
6
5
4
3
2
1
0
Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer
supported by RTL8100B(L).)
The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8100B(L) Config5 register.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
FIFOAddrPtr
LANWake
PME_STS
Symbol
MWF
UWF
LDPS
BWF
-
Reserved
Broadcast Wakeup Frame:
Multicast Wakeup Frame:
Unicast Wakeup Frame:
FIFO Address Pointer: (Realtek internal use only to test FIFO SRAM)
Link Down Power Saving mode:
LANWake signal enable/disable:
PME_Status bit: Always sticky/can be reset by PCI RST# and software.
1: Enable Broadcast Wakeup Frame with mask bytes of only DID
field = FF FF FF FF FF FF.
0: Default value. Disable Broadcast Wakeup Frame with mask bytes
of only DID field = FF FF FF FF FF FF.
field, which is a multicast address.
of only DID field, which is a multicast address.
which is its own physical address.
only DID field, which is its own physical address.
way from 1FFh and downwards. The initial FIFO address pointer is
1FFh.
are updated in ascending way from 0 and upwards. The initial FIFO
address pointer is 0.
Note: This bit does not participate in EEPROM auto-load. The FIFO
address pointers can not be reset, except initial power-on.
will power down itself (PHY Tx part & part of twister) automatically
except PHY Rx part and part of twister to monitor SD signal in case
that cable is re-connected and Link should be established again.
The power-on default value of this bit is 0.
1: Enable Multicast Wakeup Frame with mask bytes of only DID
0: Default value. Disable Multicast Wakeup Frame with mask bytes
The power-on default value of this bit is 0.
1: Enable Unicast Wakeup Frame with mask bytes of only DID field,
0: Default value. Disable Unicast Wakeup Frame with mask bytes of
The power-on default value of this bit is 0.
1: Both Rx and Tx FIFO address pointers are updated in descending
0: (Power-on) default value. Both Rx and Tx FIFO address pointers
The power-on default value of this bit is 0.
1: Disable.
0: Enable. When cable is disconnected(Link Down), the analog part
1: Enable LANWake signal.
0: Disable LANWake signal.
1: The PME_Status bit can be reset by PCI reset or by software.
0: The PME_Status bit can only be reset by software.
31
Description
RTL8100B(L)
Rev.1.41