rtl8100l Realtek Semiconductor Corporation, rtl8100l Datasheet - Page 20

• Manufacturer Part Number: rtl8100l
• Description: Fast Ethernet Controller
• Manufacturer: Realtek Semiconductor Corporation

5.10 CONFIG 0: Configuration Register 0
(Offset 0051h, R/W)
5.11 CONFIG 1: Configuration Register 1
(Offset 0052h, R/W)
2001-11-9
7-6
Bit
5
4
3
2
1
0
Bit
4-3
2-0
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R
R
R
R
-
DVRLOAD
MEMMAP
LEDS1-0
LWACT
Symbol
IOMAP
PMEn
VPD
PL1, PL0
Symbol
SCR
PCS
T10
-
Refer to the LED PIN definition. The initial value of these bits comes from the 93C46.
Driver Load: Software may use this bit to make sure that the driver has been
loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,
MEMEN, and BMEN of the PCI configuration space are written, the
RTL8100B(L) will clear this bit automatically.
LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register
are used to program the LWAKE pin’s output signal. According to the
combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,
active high, active low, positive (high) pulse, and negative (low) pulse. The
output pulse width is about 150 ms.
The default value of each of these two bits is 0, i.e., the default output signal of
LWAKE pin is an active high signal.
Memory Mapping: The operational registers are mapped into PCI memory space.
I/O Mapping: The operational registers are mapped into PCI I/O space.
Set to enable Vital Product Data: The VPD data is stored in 93C46 from within
offset 40h-7Fh.
Power Management Enable:
Writable only when 93C46CR register EEM1=EEM0=1
Configuration space offset 06H.
space offset 50H.
offset from 52H to 57H.
Configuration space offset 51H.
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.
Let C denote the Cap_ID (power management) register in the PCI Configuration
Let D denote the power management registers in the PCI Configuration space
Let E denote the Next_Ptr (power management) register in the PCI
PMEn Description
1
0
* Default value.
A=1, B=50h, C=01h, D valid, E=0
A=B=C=E=0, D not valid
Scrambler Mode: Always 0.
PCS Mode: Always 0.
10 Mbps Mode: Always 0.
Select 10 Mbps medium type: Always (PL1, PL0) = (1, 0)
Reserved
LWAKE output
LWPTN
20
0
1
Description
Positive pulse
Active high*
Description
0
LWACT
Negative pulse
Active low
RTL8100B(L)
1
Rev.1.41