upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 117

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Notes 1.
2.
3.
4.
CPU clock: f
f
f
XP
R
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
: Oscillating
: Oscillating
Status 3
(3) When “Ring-OSC cannot be stopped” is selected by mask option
XP
instruction
Interrupt
STOP
MCM0 = 1
Figure 5-13. Status Transition Diagram (3/4)
MCM0 = 0
(when subsystem clock is not used)
Interrupt
HALT
instruction
CHAPTER 5 CLOCK GENERATOR
Note 1
User’s Manual U16227EJ3V0UD
instruction
Interrupt
STOP
f
CPU clock: f
f
XP
R
STOP
: Oscillating
: Oscillating
Status 2
HALT
Note 3
HALT
instruction
Interrupt
R
Interrupt
instruction
MSTOP = 1
MSTOP = 0
STOP
Reset release
HALT instruction
Interrupt
Note 2
f
XP
: Oscillation stopped
CPU clock: f
f
Reset
R
: Oscillating
Status 1
Note 4
R
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