upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 512

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

512
16-bit
timer/
event
counter
00
(TM00)
Function
TOC00: 16-bit
timer output
control register
00
PRM00:
Prescaler mode
register 00
CR010: 16-bit
timer
capture/compare
register 010
CR000, CR010:
16-bit timer
capture/compare
registers 000,
010
PPG output
Details of
Function
Timer operation must be stopped before setting other than TOC004.
If LVS00 and LVR00 are read, 0 is read.
OSPT00 is automatically cleared after data is set, so 0 is read.
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required to write to OSPT00 successively.
Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1
simultaneously.
Perform <1> and <2> below in the following order, not at the same time.
<1> Set TOC001, TOC004, TOE00, OSPE00: Timer output operation setting
<2> Set LVS00, LVR00: Timer output F/F setting
When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the
clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the
count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00
is not guaranteed. When an external clock is used and when the Ring-OSC clock
is selected and supplied to the CPU, the operation of 16-bit timer/event counter 00
is not guaranteed, either, because the Ring-OSC clock is supplied as the sampling
clock to eliminate noise.
Always set data to PRM00 after stopping the timer operation.
If the valid edge of TI000 is to be set for the count clock, do not set the clear &
start mode using the valid edge of TI000 and the capture trigger.
If the TI000 or TI010 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the
operation of 16-bit timer counter 00 (TM00). Care is therefore required when
pulling up the TI000 or TI010 pin. However, if the TI000 pin or TI010 pin is high
level, the rising edge is not detected when re-enabling operation after the
operation has been stopped once.
When P01 is used as the TI010 valid edge input pin, it cannot be used as the
timer output (TO00), and when used as TO00, it cannot be used as the TI010 valid
edge input pin.
To change the value of the duty factor (the value of the CR010 register) during
operation, see Caution 2 in Figure 6-15 PPG Output Operation Timing.
Values in the following range should be set in CR000 and CR010:
0000H ≤ CR010 < CR000 ≤ FFFFH
The cycle of the pulse generated through PPG output (CR000 setting value + 1)
has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).
In the PPG output operation, change the pulse width (rewrite CR010) during TM00
operation using the following procedure.
<1> Disable the timer output inversion operation by match of TM00 and CR010
<2> Disable the INTTM010 interrupt (TMMK010 = 1)
<3> Rewrite CR010
<4> Wait for 1 cycle of the TM00 count clock
<5> Enable the timer output inversion operation by match of TM00 and CR010
<6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0)
<7> Enable the INTTM010 interrupt (TMMK010 = 0)
(TOC004 = 0)
(TOC004 = 1)
APPENDIX D LIST OF CAUTIONS
User’s Manual U16227EJ3V0UD
Cautions
p. 135
p. 135
p. 135
p. 135
p. 135
p. 135
p. 135
p. 136
p. 136
p. 136
p. 137
p. 137
p. 140
p. 141
p. 141
p. 142
Page
(5/22)