upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 518

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

518
A/D
converter
Function
ADS: Analog
input channel
specification
register
ADCR: A/D
conversion result
register
PFM: Power-fail
comparison
mode register
PFT: Power-fail
comparison
threshold
register
A/D conversion
operation
Power-fail
detection
function
Operating
current in
standby mode
ANI0 to ANI7
input range
Conflict
operation
Details of
Function
Be sure to clear bits 3 to 7 of ADS to 0.
If data is written to ADS, a wait cycle is generated. Do not write data to ADS
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined.
Read the conversion result following conversion completion before writing to ADM
and ADS. Using timing other than the above may cause an incorrect conversion
result to be read.
If data is read from ADCR, a wait cycle is generated. Do not read data from
ADCR when the CPU is operating on the subsystem clock and the X1 input clock
is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
If data is written to PFM, a wait cycle is generated. Do not write data to PFM
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
If data is written to PFT, a wait cycle is generated. Do not write data to PFT when
the CPU is operating on the subsystem clock and the X1 input clock is stopped.
For details, see CHAPTER 31 CAUTIONS FOR WAIT.
Make sure the period of <1> to <3> is 14
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, do not use the first conversion result after <3> in
this case.
The period from <4> to <7> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set
using FR2 to FR0.
Make sure the period of <3> to <6> is 14
It is no problem if order of <3>, <4>, and <5> is changed.
<3> must not be omitted if the power-fail function is used.
period from <7> to <11> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set
using FR2 to FR0.
The A/D converter stops operating in the standby mode. At this time, the
operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter
mode register (ADM) to 0. (refer to Figure 11-2)
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV
or higher and AV
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
ADCR read has priority. After the read operation, the new conversion result is
written to ADCR.
ADM or ADS write has priority. ADCR write is not performed, nor is the
conversion end interrupt signal (INTAD) generated.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16227EJ3V0UD
SS
or lower (even in the range of absolute maximum ratings) is
Cautions
µ
µ
s or more.
s or more.
REF
p. 229
p. 229
p. 230
p. 230
p. 231
p. 231
p. 237
p. 237
p. 237
p. 237
p. 237
p. 237
p. 237
p. 237
p. 240
p. 240
p. 240
p. 240
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