upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 514

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

514
16-bit
timer/
event
counter
00
(TM00)
Function
OVF00 flag
operation
Conflict
operation
Timer operation
Capture
operation
Compare
operation
Edge detection
Details of
Function
The OVF00 flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start
occurs on a match between TM00 and CR000, the mode in which clear & start
occurs at the TI000 valid edge, or the free-running mode
→ CR000 is set to FFFFH
→ TM00 is counted up from FFFFH to 0000H.
Even if the OVF00 flag is cleared before the next count clock is counted (before
TM00 becomes 0001H) after the occurrence of TM00 overflow, the OVF00 flag is
re-set newly and clear is disabled.
If a conflict occurs between the read period of the 16-bit timer capture/compare
register (CR000/CR010) and capture trigger input (CR000/CR010 used as capture
register), capture trigger input has priority. The data read from CR000/CR010 is
undefined.
Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit
timer capture/compare register 010 (CR010).
Regardless of the CPU’s operation mode, when the timer stops, the input signals
to the TI000/TI010 pins are not acknowledged.
The one-shot pulse output mode operates correctly only in the free-running mode
and the mode in which clear & start occurs at the TI000 valid edge. In the mode in
which clear & start occurs on a match between the TM00 register and CR000
register, one-shot pulse output is not possible because an overflow does not
occur.
If TI000 valid edge is specified as the count clock, a capture operation by the
capture register specified as the trigger for TI000 is not possible.
To ensure the reliability of the capture operation, the capture trigger requires a
pulse two cycles longer than the count clock selected by prescaler mode register
00 (PRM00).
The capture operation is performed at the falling edge of the count clock. An
interrupt request input (INTTM000/INTTM010), however, is generated at the rise
of the next count clock.
A capture operation may not be performed for CR000/CR010 set in compare
mode even if a capture trigger has been input.
If the TI000 or TI010 pin is high level immediately after system reset and the rising
edge or both the rising and falling edges are specified as the valid edge of the
TI000 or TI010 pin to enable the 16-bit timer counter 00 (TM00) operation, a rising
edge is detected immediately after the operation is enabled. Be careful therefore
when pulling up the TI000 or TI010 pin. However, if the TI000 pin or TI010 pin is
high level, the rising edge is not detected at restart after the operation has been
stopped once.
The sampling clock used to eliminate noise differs when the TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 00 (PRM00). The capture operation is only performed
when a valid level is detected twice by sampling the valid edge, thus eliminating
noise with a short pulse width.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16227EJ3V0UD
X
, and in the latter case the count clock is selected by
Cautions
p. 161
p. 161
p. 161
p. 162
p. 162
p. 162
p. 162
p. 162
p. 162
p. 162
p. 162
p. 162
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