si4330 Silicon Laboratories, si4330 Datasheet
si4330
Available stocks
Related parts for si4330
si4330 Summary of contents
Page 1
... Wireless PC peripherals Description Silicon Laboratories’ Si4330 highly integrated, single chip wireless ISM receiver is part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. ...
Page 2
... Si4330 Functional Block Diagram VDD_RF RF LDO VCO LDO AGC Control RFp RFn Mixers IF LDO BIAS VR_IF 2 RC 32K OSC PLL LDO VCO LPF CP N Digital Logic ANTDIV SPI, & Controller Digital Modem ADC PGA Preliminary Rev 0.2 30M XTAL OSC LBD PFD ...
Page 3
... Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.7. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Preliminary Rev 0.2 Si4330 Page 3 ...
Page 4
... RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3. Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13. Pin Descriptions: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 4 Preliminary Rev 0.2 ...
Page 5
... Figure 29. Sensitivity vs. Data Rate ..........................................................................................63 Figure 30. Receiver Selectivity.................................................................................................. 64 Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ........................... 65 Figure 32. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 65 Figure 33. RX LNA Matching..................................................................................................... 67 Figure 34. QFN-20 Package Dimensions................................................................................ 140 Figure 35. QFN-20 Landing Pattern Dimensions .................................................................... 140 Preliminary Rev 0.2 Si4330 5 ...
Page 6
... Table 30. Interrupt or Status 2 Bit Set/Clear Description ........................................................ 75 Table 31. Detailed Description of Status Registers when not Enabled as Interrupts ............... 75 Table 32. Internal Analog Signals Available on the Analog Test Bus .................................... 114 Table 33. Internal Digital Signals Available on the Digital Test Bus .......................................115 1 ...................................................................8 1 .......................................................................9 1 ...................................................................................10 Preliminary Rev 0.2 Si4330 6 ...
Page 7
... Crystal Oscillator and all other blocks OFF Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled Synthesizer and regulators enabled Preliminary Rev 0.2 Si4330 Min Typ Max Units 1.8 3.0 3.6 V — ...
Page 8
... Si4330 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYNTH-LB Range F SYNTH-HB Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 Phase Noise L(f M Notes: 1. All specification guaranteed by production test unless otherwise noted. ...
Page 9
... GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps kHz GFSK with BT = 0.5 IF=937 kHz Measured at RX pins (LO feed through) Preliminary Rev 0.2 Si4330 Min Typ Max Units 240 — 480 MHz 480 — ...
Page 10
... Si4330 Table 4. Auxiliary Block Specifications Parameter Symbol Temperature Sensor TS 2 Accuracy Temperature Sensor TS 2 Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock MC Output Frequency General Purpose ADC ADC 2 Accuracy General Purpose ADC ADC 2 Resolution Temp Sensor & General ...
Page 11
... OmaxLH I DRV<1:0>=HL OmaxHL I DRV<1:0>=HH OmaxHH V I < I source Omax V =1 < I sink Omax V =1 Preliminary Rev 0.2 Si4330 Min Typ Max Units — — 8 — — 8 — — – 0.6 — — DD — 0.6 –100 — 100 V – 0.6 — — ...
Page 12
... Si4330 Table 7. Absolute Maximum Ratings V to GND DD Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input Power Operating Ambient Temperature Range T Thermal Impedance JA Junction Temperature T J Storage Temperature Range T STG Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied ...
Page 13
... Production Test Conditions +25 ° +3.3 VDC DD External reference signal (XIN) = 1.0 V Production test schematic (unless noted otherwise) All RF input and output levels referred to the pins of the Si4330 (not the RF module) Extreme Test Conditions: = –40 to +85 ° +1.8 to +3.6 VDC DD External reference signal (XIN) = 0.7 to 1.6 V ...
Page 14
... Antenna diversity is completely integrated into the Si4330 and can improve the system link budget by 8–10 dB, resulting in substantial range increases depending on the environmental conditions. The Si4330 is designed to work with a microcontroller, crystal, and a few passives to create a very low cost system. Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage conditions from +1 ...
Page 15
... Depending upon the system communication protocol, the optimal trade-off between the radio wake time and power consumption can be achieved. Table 8 summarizes the modes of operation of the Si4330. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI in order to optimize the average current consumption. An “ ...
Page 16
... Select high period SW To read back data from the Si4330, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin ...
Page 17
... ADDR and read from/write to the next address. An SPI burst write transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be latched into the Si4330 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5. First Bit ...
Page 18
... Si4330 3.2. Operating Mode Control There are three primary states in the Si4330 radio state machine: SHUTDOWN, IDLE, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. ...
Page 19
... Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: Preliminary Rev 0.2 Si4330 19 ...
Page 20
... Si4330 1. Enable the Main Digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”). 5. Wait until PLL settles to required receive frequency (controlled by timer). ...
Page 21
... Interrupts The Si4330 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h– ...
Page 22
... Si4330 3.5. System Timing The system timing for RX mode is shown in Figure small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device. The relevant system timing registers are shown below. Add R/W Function/Description ...
Page 23
... The following information can be used to calculated these values manually. 3.6.1. Frequency Programming In order to receive an RF signal, the desired channel frequency, fcarrier, must be programmed into the Si4330. Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier ...
Page 24
... Si4330 fb[4:0] Value The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture ...
Page 25
... Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4330 often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h– ...
Page 26
... Si4330 The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. FIFO Mode" on page 29 for further details. Add R/W Function/Description 71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] ...
Page 27
... Hz ( hbsel ) 1 fo DesiredOff set 156 . hbsel ) fo[6] fo[5] fo[4] fo[3] (Rb = 100 kHz kHz) - 100 Frequency Offset (kHz) Preliminary Rev 0.2 Si4330 [ : POR Notes Def. fo[2] fo[1] fo[0] 00h 73 00h AFC Disable AFC Enable 27 ...
Page 28
... Si4330 The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in “Register 1Dh. AFC Loop Gearshift Override,” on page 92), the Frequency Offset shows the results of the AFC algorithm for the current receive slot. When selecting the preamble length, the length needs to be long enough to settle the AFC ...
Page 29
... Operating Mode and Function Control 1" mode the rxon bit will only be cleared if ipkvalid occurs. A CRC, Header, or Sync error will generate an interrupt and the microcontroller will need to decide on the next action. Preliminary Rev 0.2 Si4330 29 ...
Page 30
... Si4330 5. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm ...
Page 31
... Frequency Band Select" VCO is utilized to help avoid problems due to frequency pulling, especially when turning on the integrated Power Amplifier. In receive mode, the LO frequency is automatically shifted downwards (without reprogramming) by the IF frequency of 937.5 kHz, allowing receive CP LPF VCO N Preliminary Rev 0.2 Si4330 TM is integrated to Selectable RX Divider 31 ...
Page 32
... Capacitance 5.8. Regulators There are a total of six regulators integrated onto the Si4330. With the exception of the IF and Digital all regulators are designed to operate with only internal decoupling. The IF and Digital regulators both require an external 1 µF decoupling capacitor. All of the regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V, and produce a nominal regulated output voltage of +1.7 V ± ...
Page 33
... Interrupt Status registers. RX FIFO RX FIFO Almost Full Threshold Figure 11. FIFO Threshold rxmpk Reserved Preliminary Rev 0.2 Si4330 POR Def. enldm ffclrrx Reserved 00h POR Def. 37h 33 ...
Page 34
... Si4330 6.2. Packet Configuration When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access Control" through “Register 39h. Synchronization Word 0,” on page 107 and “Register 3Fh. Check Header 3,” on page 108 through “Register 4Bh. Received Packet Length,” on page 112 control the configuration, status, and decoded RX packet data for Packet Handling ...
Page 35
... Data Write Pointer H L Data 63 63 set option set option set — set — set — — — for sync-detection Preliminary Rev 0.2 Si4330 txhdlen > 0 fixpklen Data Data Data FIFO Addr Data H L Data Write ...
Page 36
... Si4330 Add R/W Function/Description D7 30 R/W Data Access Control enpacrx 31 R EzMAC status Reserved 32 R/W Header Control 1 bcen[3] 33 R/W Header Control 2 Reserved 34 R/W Preamble Length prealen[7] 35 R/W Preamble Detection Control preath[4] 36 R/W Sync Word 3 sync[31] 37 R/W Sync Word 2 sync[23] 38 R/W Sync Word 1 sync[15] 39 R/W Sync Word 0 sync[7] 3A–3E R/W Reserved 3F R/W Check Header 3 ...
Page 37
... Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC 6.5. Preamble Detector The Si4330 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in “6.2. Packet Configuration”. The preamble detection threshold, preath[4:0] as set in "Register 35h. Preamble Detection Control 1" ...
Page 38
... Si4330 Table 14. Minimum Receiver Settling Time Mode receiver settling time (G)FSK AFC Disabled (G)FSK AFC Enabled (G)FSK AFC Disabled +Antenna Diversity Enabled (G)FSK AFC Enabled +Antenna Diversity Enabled OOK OOK + Antenna Diversity Enabled Note: The recommended preamble length and the preamble detection threshold may be shortened when occasional packet errors are tolerable ...
Page 39
... Preliminary Rev 0.2 Si4330 rxosr[10:0] ncoff[19:0] crgain[10:0] 20,21h 21,22,23h 24,25h 0FA 08312 06B 0D0 09D49 0A0 683 013A9 005 068 13A93 278 341 02752 00A 068 13A93 4EE 1A1 04EA5 ...
Page 40
... Si4330 7.1.1. Advanced FSK and GFSK Settings In nearly all cases, the information in Table 15, “RX Modem Configurations for FSK and GFSK,” on page 39 can be used to determine the required FSK and GFSK modem parameters. The section includes a more detailed discussion of the various modem parameters to allow for experienced designers to further configure the modem performance ...
Page 41
... Preliminary Rev 0.2 Si4330 dwn3_bypass filset 1C-[7] 1C-[3: ...
Page 42
... Si4330 7.2. Modem Settings for OOK The Si4330 is configured for OOK mode by setting the modtyp[1:0] field to OOK in "Register 71h. Modulation Mode Control 2". In OOK mode, the following parameters can be configured: data rate, manchester coding, channel filter bandwidth, and the clock recovery oversampling rate. ...
Page 43
... enmanch 20 ndec enmanch ) 2 500 1 2 dwn 3 _ bypass 16 2 2 crgain rxosr Preliminary Rev 0.2 Si4330 exp 43 ...
Page 44
... Si4330 Table 19. RX Modem Configuration for OOK with Manchester Disabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters dwn3_bypass [kbps] [kHz] 1Ch 1 1.2 110 0 1.2 335 1 1.2 420 1 1.2 620 1 2.4 335 1 4.8 335 1 9.6 335 1 10 335 1 15 335 1 19.2 335 1 20 335 1 30 335 1 38 ...
Page 45
... Auxiliary Functions 8.1. Smart Reset The Si4330 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances. Reset will be initiated if any of the following conditions occur: Initial power on, when VDD starts from 0V: reset is active till VDD reaches V ...
Page 46
... If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the Si4330 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called Enable Low Frequency Clock and is enabled by the enlfc bit ...
Page 47
... BAT Ref MUX BAT REFSEL<1:0> adcsel[2] adcsel[1] adcsel[0] adcref[1] adcoffs[3] adc[7] adc[6] adc[5] adc[4] adc[3] Preliminary Rev 0.2 Si4330 8-bit ADC VMEAS<7:0> POR Def. adcref[0] adcgain[1] adcgain[0] 00h adcoffs[2] adcoffs[1] adcoffs[0] 00h adc[2] adc[1] adc[0] — 47 ...
Page 48
... Si4330 8.3.1. ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this configuration will utilize two GPIO pins. The supply source of the bridge and chip should be the same to eliminate the measuring error caused by battery discharging ...
Page 49
... The offset compensation is VDD proportional, so the VDD change has no influence on the measured value. adcoffs[ Input Offset 0. –0.84 % Figure 20. ADC Differential Input Offset for Sensor Offset Coarse Compensation Input Offset (% of VDD adcoffs[2: –(8 – adcoffs[2:0]) x 0.12 adcoffs[2:0] x 0.12 8 Preliminary Rev 0.2 Si4330 adcoffs[3: ...
Page 50
... Si4330 8.4. Temperature Sensor An analog temperature sensor is integrated into the chip. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through " ...
Page 51
... Temperature Measurement with ADC8 300 250 200 150 100 50 0 -40 - Temperature [Celsius] Figure 21. Temperature Ranges using ADC8 Preliminary Rev 0.2 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 100 Si4330 51 ...
Page 52
... Si4330 8.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller will then need to verify the interrupt by reading " ...
Page 53
... wtr[3] wtr[2] wtr[1] wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] Preliminary Rev 0.2 Si4330 POR Def. wtr[0] wtd[1] wtd[0] 00h 00h wtm[2] wtm[1] wtm[0] 00h wtv[10] wtv[9] wtv[8] — wtv[2] ...
Page 54
... Si4330 WUT Period GPIOX=00001 nIRQ SPI Interrupt Read Chip State Sleep Ready 1mA Current Consumption WUT Period GPIOX=00001 nIRQ SPI Interrupt Read Chip State Current Consumption Figure 22. WUT Interrupt and WUT Operation 54 Interrupt Enable enwut=1 (Reg 06h) Sleep Ready Sleep 1mA ...
Page 55
... The time of the TLDC is determined by the formula below: TLDC ldc [ : 768 Figure 23. Low Duty Cycle Mode Preliminary Rev 0.2 Si4330 ms 55 ...
Page 56
... Si4330 8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, Antenna Diversity Switch control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. ...
Page 57
... Antenna Diversity Algorithm in Beacon Mode antdiv[2] antdiv[1] antdiv[0] rxmpk Reserved enldm ffclrrx Reserved Table 23. Antenna Diversity Control RX State GPIO Ant2 Preliminary Rev 0.2 Si4330 POR Def. 00h Non RX State GPIO Ant1 GPIO Ant2 ...
Page 58
... Si4330 8.10. RSSI and Clear Channel Assessment The RSSI (Received Signal Strength Indicator) signal is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 24 demonstrates the relationship between input power level and RSSI value. The RSSI may be read at anytime, but an incorrect error may rarely occur ...
Page 59
... Reference Design 1 R 100k VDD VDD GND NSEL _DIG VR 16 NIRQ _2 GPIO 17 XOUT _1 GPIO 18 XIN _0 GPIO 19 SDN ADC_REF PWRDN VDD VDD + 100k +5V EEPROM +5V 100k 4 R +5V Preliminary Rev 0.2 Si4330 4 Array 10k ...
Page 60
... C11 2.2 µF CPOL-USCT3216 C12 100 pF C-USC0603K C13 1 µF C-USC0603K C14 100 pF C-USC0603K C18 100 nF C-USC0603K C23 100 nF C-USC0603K CS1 CON40-0 CON40-0 IC1 Si4330 IC IC2 25AA040ST 25AA040ST L6 * INDUCTCOILCRAFT-0603 Q1 30 MHz CRYSTAL Q2 32.7 kHz CRYSTAL R1 100 k R-US_R0603 R2 10 k R-US_R0603 R4 100 k R-US_R0603 R5 10 k ...
Page 61
... Figure 26. Receiver—Top Figure 27. Receiver—Top Silkscreen Preliminary Rev 0.2 Si4330 61 ...
Page 62
... Si4330 Note: The reference design shown above is the that of the standard testcard that may be ordered directly from Silicon Labs. Within this reference design is a EEPROM called the EBID (Evaluation Board IDentification). The EBID is used by other Silicon Labs development tools and is not required on customer designs. ...
Page 63
... Note: Sensitivity is BER measured, GFSK modulation 0. Sensitivity vs. Data Rate Measured at RX SMA Connector Input 10 kbps Data Rate Figure 29. Sensitivity vs. Data Rate Preliminary Rev 0.2 Si4330 100 kbps 1000 kbps 63 ...
Page 64
... Si4330 Adjacent Channel Selectivity at 50 kbps Measured at RX SMA Connector Input -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB -1.00 -0.75 MHz MHz Adjacent Channel Selectivity at 50 kbps (log scale) Measured at RX SMA Connector Input -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB ...
Page 65
... Si4330 Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz Figure 32. Synthesizer Phase Noise (VCOCURR = 11) Preliminary Rev 0.2 Si4330 65 ...
Page 66
... Si4330 11. Application Notes 11.1. Crystal Selection The recommended crystal parameters are given in Table 25. Table 25. Recommended Crystal Parameters Frequency ESR 30 MHz 60 Ω The internal XTAL oscillator will work over a range for the parameters of ESR, CL, C0, and ppm accuracy. Extreme values may affect the XTAL start-up and sensitivity of the link. For questions regarding the use of a crystal parameters greatly deviating from the recommend values listed above, please contact customer support. The crystal used for engineering evaluation and the reference design is the SIWARD – ...
Page 67
... Matching Network Design 11.3.1. RX LNA Matching Table 26. RX Matching for Different Bands Freq Band 915 MHz 868 MHz 433 MHz 315 MHz Figure 33. RX LNA Matching C1 L 6.8 pF 11.0 nH 6.8 pF 11.0 nH 10.0 pF 33.0 nH 15.0 pF 47.0 nH Preliminary Rev 0.2 Si4330 C2 3.3 pF 3.9 pF 4 ...
Page 68
... Si4330 12. Reference Material 12.1. Complete Register Table and Descriptions Add R/W Function/Desc 00 R Device Type 01 R Device Version 02 R Device Status 03 R Interrupt Status Interrupt Status 2 05 R/W Interrupt Enable 1 06 R/W Interrupt Enable 2 07 R/W Operating & Function Control 1 08 R/W Operating & Function Control 2 ...
Page 69
... Reserved Reserved Reserved fhch[7] fhch[6] fhch[5] fhs[7] fhs[6] fhs[5] 15.4 Length Reserved Reserved Reserved Reserved rxafthr[5] fifod[7] fifod[6] fifod[5] Preliminary Rev 0.2 Si4330 Data chhd[12] chhd[11] chhd[10] chhd[9] chhd[4] chhd[3] chhd[2] chhd[1] hden[28] hden[27] hden[26] hden[25] hden[20] hden[19] hden[18] hden[17] hden[12] ...
Page 70
... Si4330 Register 00h. Device Type Code (DT) Bit D7 D6 Reserved Name R Type Reset value = 00001000 Bit Name 7:5 Reserved Reserved. 4:0 dt[4:0] Device Type Code. EZRadioPRO: 01000. Register 01h. Version Code (VC) Bit D7 D6 Reserved Name R Type Reset value = xxxxxxxx Bit Name 7:5 Reserved Reserved. 4:0 vc[4:0] Version Code. ...
Page 71
... RX FIFO Underflow Status. 5 rxffem RX FIFO Empty Status. 4 headerr Header Error Status. Indicates if the received packet has a header check error. 3:2 Reserved Reserved. 1:0 cps[1:0] Chip Power State. 00: Idle State 01: RX State rxffem headerr Reserved Function Preliminary Rev 0.2 Si4330 Reserved cps[1: ...
Page 72
... Si4330 Register 03h. Interrupt/Status 1 Bit D7 D6 ifferr Reserved Name R R Type Reset value = xxxxxxxx Bit Name 7 ifferr FIFO Underflow/Overflow Error. When set to 1 the RX FIFO has overflowed or underflowed. 6:5 Reserved Reserved. 4 irxffafull RX FIFO Almost Full. When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller ...
Page 73
... Sync Word for the next packet. 0 icrcerror Goes High once the CRC computed during RX differs from the CRC sent in the packet by the TX cleaned once we start receiving new data in the next packet. Set/Clear Conditions Set/Clear Conditions Preliminary Rev 0.2 Si4330 73 ...
Page 74
... Si4330 Register 04h. Interrupt/Status 2 Bit D7 D6 iswdet ipreaval Name R R Type Reset value = xxxxxxxx Bit Name 7 iswdet Sync Word Detected. When a sync word is detected this bit will be set ipreaval Valid Preamble Detected. When a preamble is detected this bit will be set to 1. ...
Page 75
... Probably the status is cleared once the battery is replaced. 1 ichiprdy Chip ready goes high once we enable the xtal, RX, and a settling time for the Xtal clock elapses. The status stay high unless we go back to Idle mode. 0 ipor Power on status. Set/Clear Conditions Set/Clear Conditions Preliminary Rev 0.2 Si4330 75 ...
Page 76
... Si4330 Register 05h. Interrupt Enable 1 Bit D7 D6 enfferr Reserved Name R/W R/W Type Reset value = 00000000 Bit Name 7 enfferr Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled. 6:5 Reserved Reserved. 4 enrxffafull Enable RX FIFO Almost Full. When set to 1 the RX FIFO Almost Full interrupt will be enabled. ...
Page 77
... When set to 1 the Low Battery Detect interrupt will be enabled. 1 enchiprdy Enable Chip Ready (XTAL). When set to 1 the Chip Ready interrupt will be enabled. 0 enpor Enable POR. When set to 1 the POR interrupt will be enabled enpreainval enrssi enwut R R R/W Function Preliminary Rev 0.2 Si4330 enlbd enchiprdy enpor R/W R/W R/W 77 ...
Page 78
... Si4330 Register 07h. Operating Mode and Function Control 1 Bit D7 D6 swres enlbd Name R/W R/W Type Reset value = 00000001 Bit Name 7 swres Software Register Reset Bit. This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register. The RESET is accomplished by setting swres = 1 ...
Page 79
... This has two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the contents of the RX FIFO. 0 Reserved Reserved rxmpk Reserved R/W R/W Function non RX state GPIO Ant2 Preliminary Rev 0.2 Si4330 enldm ffclrrx Reserved R/W R/W R/W GPIO Ant1 GPIO Ant2 ...
Page 80
... Si4330 Register 09h. 30 MHz Crystal Oscillator Load Capacitance Bit D7 D6 xtalshft Name R/W Type Reset value = 01111111 Bit Name 7 xtalshft Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0]. 6:0 xlc[6:0] Tuning Capacitance for the 30 MHz XTAL ...
Page 81
... RC Oscillator. The mclk[2:0] setting is only valid when xton = 1 except the 111. 000: 30 MHz 001: 15 MHz 010: 10 MHz 011: 4 MHz 100: 3 MHz 101: 2 MHz 110: 1 MHz 111: 32.768 kHz clkt[1:0] enlfc R/W R/W Function Preliminary Rev 0.2 Si4330 mclk[2:0] R/W 81 ...
Page 82
... Si4330 Register 0Bh. GPIO Configuration 0 Bit D7 D6 gpiodrv0[1:0] Name R/W Type Reset value = 00000000 Bit Name 7:6 gpiodrv0[1:0] GPIO Driving Capability Setting. 5 pup0 Pullup Resistor Enable on GPIO0. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. ...
Page 83
... Antenna 1 Switch used for antenna diversity (output) 11000: Antenna 2 Switch used for antenna diversity (output) 11001: Valid Preamble Detected (output) 11010: Invalid Preamble Detected (output) 11011: Sync Word Detected (output) 11100: Clear Channel Assessment (output) 11101: VDD else : GND pup1 R/W Function Preliminary Rev 0.2 Si4330 gpio1[4:0] R/W 83 ...
Page 84
... Si4330 Register 0Dh. GPIO Configuration 2 Bit D7 D6 gpiodrv2[1:0] Name R/W Type Reset value = 00000000 Bit Name 7:6 gpiodrv2[1:0] GPIO Driving Capability Setting. 5 pup2 Pullup Resistor Enable on GPIO2. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. ...
Page 85
... If the GPIO0 is configured direct output then the value on the GPIO pin can be set here. If the GPIO0 is configured direct input then the value of the pin can be read here extitst[1] extitst[0] itsdo R R R/W Function Preliminary Rev 0.2 Si4330 dio2 dio1 dio0 R/W R/W R/W 85 ...
Page 86
... Si4330 Register 0Fh. ADC Configuration Bit D7 D6 adcstart/ Name adcdone R/W Type Reset value = 00000000 Bit Name 7 adcstart/adc- ADC Measurement Start Bit. done Reading this bit gives 1 if the ADC measurement cycle has been finished. 6:4 adcsel[2:0] ADC Input Source Selection. The internal 8-bit ADC input source can be selected as follows: ...
Page 87
... The offset can be calculated as Offset = adcoffs[2:0] x VDD / 1000; MSB = adcoffs[3] = Sign bit. Register 11h. ADC Value Bit D7 D6 Name Type Reset value = xxxxxxxx Bit Name 7:0 adc[7:0] Internal 8 bit ADC Output Value Function adc[7:0] R Function Preliminary Rev 0.2 Si4330 adcoffs[3:0] R ...
Page 88
... Si4330 Register 12h. Temperature Sensor Calibration Bit D7 D6 tsrange[1:0] Name R/W Type Reset value = 00100000 Bit Name 7:6 tsrange[1:0] Temperature Sensor Range Selection. (FS range is 0..1024 mV) –40 C (full operating range), with 0.5 C resolution (1 LSB in the 8-bit 00: ADC) –40 C, with 1 C resolution (1 LSB in the 8-bit ADC) ...
Page 89
... The period of the wake-up timer can be calculated Function 32.768 ms allowed, and the WUT wtm[15:8] R/W Function 32.768 ms. WUT wtm[7:0] R/W Function 32.768 ms. WUT Preliminary Rev 0.2 Si4330 wtr[4:0] R ...
Page 90
... Si4330 Register 17h. Wake-Up Timer Value 1 Bit D7 D6 Name Type Reset value = xxxxxxxx Bit Name 7:0 wtm[15:8] Wake Up Timer Current Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as T Register 18h. Wake-Up Timer Value 2 Bit D7 D6 Name Type Reset value = xxxxxxxx ...
Page 91
... Bit Name 7:5 Reserved Reserved. 4:0 vbat[4:0] Battery Voltage Level. The battery voltage is converted bit ADC. In Sleep Mode the register is updated in every other states it measures continuously Function = 1.7 + lbdt x 50 mV. threshold Function Preliminary Rev 0.2 Si4330 lbdt[4:0] R vbat[4: ...
Page 92
... Si4330 Register 1Ch. IF Filter Bandwidth Bit D7 D6 dwn3_bypass Name R/W Type Reset value = 00000001 Bit Name 7 dwn3_bypass Bypass Decimator by 3 (if set). 6:4 ndec_exp[2:0] IF Filter Decimation Rates. 3:0 filset[3:0] IF Filter Coefficient Sets. Defaults are for kbps and kHz kHz. Register 1Dh. AFC Loop Gearshift Override ...
Page 93
... Short Wait Periods after AFC Correction. Used before preamble is detected. Short wait = (RegValue + AFC correction will occur before preamble detect, i.e. AFC will be disabled. 2:0 anwait[2:0] Antenna Switching Wait Time. Value corresponds to number of bits shwait[2:0] R/W Function Preliminary Rev 0.2 Si4330 anwait[2:0] R/W If set to 0 then ...
Page 94
... Si4330 Register 1Fh. Clock Recovery Gearshift Override Bit D7 D6 Reserved rxready Name R/W R/W Type Reset value = 00000011 Bit Name 7 Reserved Reserved. 6 rxready Improves Receiver Noise Immunity when in Direct Mode recommended to set this bit after preamble is detected. When in FIFO mode this bit should be set to “ ...
Page 95
... rxosr[7:0] R/W Function ndec_exp 500 1 2 dwn 3 _ bypass rxosr ndec _ exp enmanch Preliminary Rev 0.2 Si4330 RX_DR). The ndec_exp and the ...
Page 96
... Si4330 Register 21h. Clock Recovery Offset 2 Bit D7 D6 rxosr[10:8] Name R/W Type Reset value = 00000001 Bit Name 7:5 rxosr[10:8] Oversampling Rate. Upper bits. 4 stallctrl Used for BCR Purposes. 3:0 ncoff[19:16] NCO Offset. See formula above. The offset can be calculated as follows: The default values for register 20h to 23h gives 40 kbps RX_DR with Manchester coding is disenabled. ...
Page 97
... Name Type Reset value = 10001111 Bit Name 7:0 crgain[7:0] Clock Recovery Timing Loop Gain ncoff[7:0] R/W Function Reserved R/W Function 15 enmanch + crgain ----------------------------------------------------------------------- - rxosr crgain[7:0] R/W Function Preliminary Rev 0.2 Si4330 crgain[10:8] R/W ...
Page 98
... Si4330 Register 26h. Received Signal Strength Indicator Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 rssi[7:0] Received Signal Strength Indicator Value. Register 27h. RSSI Threshold for Clear Channel Indicator Bit D7 D6 Name Type Reset value = 00011110 Bit Name 7:0 rssith[7:0] RSSI Threshold. ...
Page 99
... AFC loop correction values [9:2] (MSBs only). Values are updated once, after sync word is found during receiving. See also address 2Ch adrssi2[7:0] R Function Afclim[7:0] R/W Function 3 500[kHz] ook _ cnt _ val enmanch afc_corr[9:2] R Function Preliminary Rev 0.2 Si4330 ...
Page 100
... Si4330 Register 2Ch. OOK Counter Value 1 Bit D7 D6 afc_corr[1:0] Name R Type Reset value = 00101100 Bit Name 7:6 afc_corr[1:0] AFC Correction Values. AFC loop correction values [1:0] (LSBs). Values are updated once, after sync word is found during receiving. See also address 2Bh. 5 ookfrzen OOK Freeze. ...
Page 101
... Reserved Reserved. 3 Reserved Reserved. 2 encrc CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set. 1:0 crc[1:0] CRC Polynomial Selection. 00: CCITT 01: CRC-16 (IBM) 10: IEC-16 11: Biacheva attack[2:0] R/W Function crcdonly Reserved Reserved R/W R/W R/W Function Preliminary Rev 0.2 Si4330 decay[3:0] R encrc crc[1:0] R/W R/W 101 ...
Page 102
... Si4330 ® Register 31h. EZMAC Status Bit D7 D6 Reserved rxcrc1 Name R R Type Reset value = 00000000 Bit Name 7 Reserved Reserved. 6 rxcrc1 If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error. Packet Searching . 5 pksrch When pksrch = 1 the radio is searching for a valid packet. ...
Page 103
... Broadcast address enable for header byte 0. Broadcast address enable for header byte 1. Broadcast address enable for header bytes 0 & 1. … No Received Header check Received Header check for byte 0. Received Header check for bytes 1. Received header check for bytes 0 & 1. … Preliminary Rev 0.2 Si4330 hdch[3:0] R/W 103 ...
Page 104
... Si4330 Register 33h. Header Control 2 Bit D7 D6 Reserved Name R Type Reset value = 00100010 Bit Name 7 Reserved Reserved. 6:4 hdlen[2:0] Header Length. Length of header used if packet handler is enabled for RX (enpacrx). Headers are received in descending order. 000: 001: 010: 011: 100: 3 fixpklen Fix Packet Length. ...
Page 105
... Reset value = 00101010 Bit Name 7:3 preath[4:0] Number of nibbles processed during detection. 2:0 rssi_offset[2:0] rssi_offset[2:0] Value added as offset to RSSI calculation. Every increment in this register results in an increment the RSSI prealen[7:0] R/W Function preath[4:0] R/W Function Preliminary Rev 0.2 Si4330 rssi_offset[2:0] R/W 105 ...
Page 106
... Si4330 Register 36h. Synchronization Word 3 Bit D7 D6 Name Type Reset value = 00101101 Bit Name 7:0 sync[31:24] Synchronization Word byte of the synchronization word. Register 37h. Synchronization Word 2 Bit D7 D6 Name Type Reset value = 11010100 Bit Name 7:0 sync[23:16] Synchronization Word byte of the synchronization word. ...
Page 107
... Packet Length for RX mode. Check Header bytes are checked against the corresponding bytes in the Received Header if the check is ® enabled in "Register 31h. EZMAC sync[7:0] R/W Function pklen[7:0] R/W Function Status". Preliminary Rev 0.2 Si4330 107 ...
Page 108
... Si4330 Register 3Fh. Check Header 3 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 chhd[31:24] Check Header byte of the check header. Register 40h. Check Header 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 chhd[23:16] Check Header byte of the check header. ...
Page 109
... Register 44h. Header Enable 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 hden[23:16] Header Enable byte of the check header chhd[7:0] R/W Function hden[31:24] R/W Function hden[23:16] R/W Function Preliminary Rev 0.2 Si4330 109 ...
Page 110
... Si4330 Register 45h. Header Enable 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 hden[15:8] Header Enable byte of the check header. Register 46h. Header Enable 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 hden[7:0] Header Enable byte of the check header. ...
Page 111
... Register 4Ah. Received Header 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 rxhd[7:0] Received Header byte of the received header rxhd[23:16] R Function rxhd[15:8] R Function rxhd[7:0] R Function Preliminary Rev 0.2 Si4330 111 ...
Page 112
... Si4330 Register 4Bh. Received Packet Length Bit D7 D6 Name Type Reset value = 11111111 Bit Name 7:0 rxplen[7:0] Length Byte of the Received Packet during fixpklen = 0 . (Specifies the number of Data bytes in the last received packet) This will be relevant ONLY if fixpklen (address 33h, bit[3]) is low during the receive time. If fixpklen is high, then the number of received Data Bytes can be read from the pklen register (address h3E) ...
Page 113
... Register 50h. Analog Test Bus Select Bit D7 D6 Reserved Name R/W Type Reset value = 00000000 Bit Name 7:5 Reserved Reserved. 4:0 atb[4:0] Analog Test Bus. The selection of internal analog testpoints that are muxed onto TESTp and TESTn Function Preliminary Rev 0.2 Si4330 atb[4:0] R/W 113 ...
Page 114
... Si4330 Table 32. Internal Analog Signals Available on the Analog Test Bus atb[4: 114 GPIOx GPIOx MixIp MixIn MixQp MixQn PGA_Ip PGA_In PGA_QP PGA_Qn ADC_vcm ADC_vcmb ADC_ipoly10u ADC_ref ...
Page 115
... VCO bias shunt enable frac_div_en fractional divider enable pll_pfd_down PFD down signal pll_en PLL enable: TUNE state pll_lock_detect PLL lock detect pwst[1] internal power state Preliminary Rev 0.2 Si4330 GPIO2 Signal clk_base timebase clock tm1sec 1 sec timebase adc_done aux. ADC measurement done ...
Page 116
... Si4330 Table 33. Internal Digital Signals Available on the Digital Test Bus (Continued) dtb[4:0] GPIO0 Signal 30 xok chip ready: READY state 31 ts_en temperature sensor enable 32 ch_freq_req frequency change request 33 retran_req retransmission request 34 pa_on_trig PA ON trigger 35 tx_shdwn TX shutdown 36 pk_sent_dly delayed packet sent 37 tx_en TX enable: TX state ...
Page 117
... Invalid Preamble Threshold. 1 ldo_pa_boost LDO PA Boost. 0 pa_vbias_boost PA VBIAS Boost. Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold Bit Rate period pllts[4:0] R/W Function ). inv_pre_th R/W Function Preliminary Rev 0.2 Si4330 = pllt0 R ldo_pa_boost pa_vbias_boost R/W R/W 117 ...
Page 118
... Si4330 Register 55h. Calibration Control Bit D7 D6 Reserved xtalstarthalf Name R R/W Type Reset value = x1x00100 Bit Name 7 Reserved Reserved. 6 xtalstarthalf If Set, the Xtal Wake Time Period is Halved. 5 adccaldone Delta-sigma ADC Calibration Done. Reading this bit gives 1 if the calibration process has been finished. ...
Page 119
... Delta-Sigma Reference Clock Source Selection 1: 10 MHz 0: PLL 1 refclkinv Delta-Sigma Reference Clock Inversion Enable. 0 distogg If reset, the discriminator toggling is disabled dttype oscdeten ookth R/W R/W R/W Function Preliminary Rev 0.2 Si4330 refclksel refclkinv distogg R/W R/W R/W 119 ...
Page 120
... Si4330 Register 57h. Charge Pump Test Bit D7 D6 pfdrst fbdiv_rst Name R/W R/W Type Reset value = 00000000 Bit Name 7 pfdrst Direct Control to Analog. 6 fbdiv_rst Direct Control to Analog. 5 cpforceup Charge Pump Force Up. 4 cpforcedn Charge Pump Force Down. 3 cdconly Charge Pump DC Offset Only. 2:0 cdcurr[2:0] Charge Pump DC Current Selection ...
Page 121
... Reserved vcocorrov Name R/W R/W Type Reset value = 00000011 Bit Name 7 Reserved Reserved. 6 vcocorrov VCO Current Correction Override. 5:2 vcocorr[3:0] VCO Current Correction Value. 1:0 vcocur[1:0] VCO Current Trim Value d3trim[1:0] d2trim[1:0] R/W R/W Function vcocorr[3:0] R/W Function Preliminary Rev 0.2 Si4330 d1p5trim[1:0] R vcocur[1:0] R/W 121 ...
Page 122
... Si4330 Register 5Bh. VCO Calibration/Override Bit D7 D6 vcocalov/vcdone Name R/W Type Reset value = 00000000 Bit Name 7 vco- VCO Calibration Override/Done. calov/vcdone When vcocalov = 0 the internal VCO calibration results may be viewed by reading the vcocal register. When vcocalov = 1 the VCO results may be overridden externally through the SPI by writing to the vcocal register ...
Page 123
... Buffer 4 Enable Override. 3 enbf3 Buffer 3 Enable Override. 2 enbf11 Buffer 1_1 Enable Override. 1 enbf2 Buffer 2 Enable Override. 0 pllreset PLL Reset Enable Override enpga Reserved enbf5 R/W R/W R/W Function enmx3 enbf4 enbf3 R/W R/W R/W Function Preliminary Rev 0.2 Si4330 endv32 enbf12 enmx2 R/W R/W R enbf11 enbf2 pllreset R/W R/W R/W 123 ...
Page 124
... Si4330 Register 5Fh. Block Enable Override 3 Bit D7 D6 enfrdv endv31 Name R/W R/W Type Reset value = 00000000 Bit Name 7 enfrdv Fractional Divider Enable Override. 6 endv31 Divider 3_1 Enable Override. 5 endv2 Divider 2 Enable Override. 4 endv1p5 Divider 1.5 (div-by-1.5) Enable Override. 3 dvbshunt VCO Bias Shunt Enable Override Mode. ...
Page 125
... Output Buffer Enable. This bit is active only if the bufovr bit is set chfilval[5:0] R/W Function clkhyst enbias2x R/W R/W Function Preliminary Rev 0.2 Si4330 enamp2x bufovr enbuf R/W R/W R/W 125 ...
Page 126
... Si4330 Register 63h. RC Oscillator Coarse Calibration/Override Bit D7 D6 rccov Name R/W Type Reset value = 00000000 Bit Name 7 rccov RC Oscillator Coarse Calibration Override. When rccov = 0 the internal Coarse Calibration results may be viewed by reading the rcccal register. When rccov = 1 the Coarse results may be overridden externally through the SPI by writing to the rcccal register ...
Page 127
... Xtal Override Enable Value. 5 ents Temperature Sensor Enable. 4 enrc32 32K Oscillator Enable. 3 Reserved Reserved. 2:0 diglvl Digital LDO Level Setting envcoldo enifldo enrfldo R/W R/W R/W Function ents enrc32 Reserved R/W R/W R Function Preliminary Rev 0.2 Si4330 enpllldo endigldo endigpwdn R/W R/W R diglvl R/W 127 ...
Page 128
... Si4330 Register 67h. Delta-Sigma ADC Tuning 1 Bit D7 D6 adcrst enrefdac Name R/W R/W Type Reset value = 00011101 Bit Name 7 adcrst Delta-Sigma ADC Reset. 6 enrefdac Delta-Sigma ADC Reference DAC Enable Override. 5 enadc Delta-Sigma ADC Enable Override. 4 adctuneovr Resonator RC Calibration Value Override Enable. 3:0 adctune[3:0] Resonator RC Calibration Value. ...
Page 129
... LNA Gain Compensation. This bit is used for smoothing RSSI value when LNA gain is switched. 1:0 pgath[1:0] Window Comparator Reference Voltage Adjust in the PGA agcen lnagain R/W R/W Function 1 – max. gain = lnacomp[3:0] R/W Function Preliminary Rev 0.2 Si4330 pga[3:0] R pgath[1:0] R/W 129 ...
Page 130
... Si4330 Register 6Fh. TX Data Rate 0 Bit D7 D6 Name Type Reset value = 00111101 Bit Name 7:0 txdr[7:0] Data Rate Lower Byte. See formula above. Defaults = 40 kbps. Register 70h. Modulation Mode Control 1 Bit D7 D6 Reserved Name R Type Reset value = 00001100 Bit Name 7:6 Reserved Reserved. ...
Page 131
... D7 D6 Reserved Name R/W Type Reset value = 00000000 Bit Name 7:4 Reserved Reserved. 3 eninv RX Data. 2 fd[8] MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation". 1:0 Reserved Reserved. The frequency deviation can be calculated 625 Hz x fd[8:0 Reserved eninv R/W R/W Function Preliminary Rev 0.2 Si4330 fd[8] Reserved R/W R/W 131 ...
Page 132
... Si4330 Register 72h. Frequency Deviation Bit D7 D6 Name Type Reset value = 00100000 Bit Name 7:0 fd[7:0] Frequency Deviation Setting. See formula above. Note: It's recommended to use modulation index higher (maximum allowable modulation index is 32). The modulation index is defined by 2F were modulation index is defined by F Register 73h ...
Page 133
... Parameters 79h and 7Ah Reserved R Function hbsel R/W Function 10) [kHz], hch hs Preliminary Rev 0.2 Si4330 fo[9:8] R fb[4:0] R/W and f come from register hch hs 133 ...
Page 134
... Si4330 Register 76h. Nominal Carrier Frequency Bit D7 D6 Name Type Reset value = 10111011 Bit Name 7:0 fc[15:8] Nominal Carrier Frequency Setting. See formula above. Register 77h. Nominal Carrier Frequency Bit D7 D6 Name Type Reset value = 10000000 Bit Name 7:0 fc[7:0] Nominal Carrier Frequency Setting. See formula above. ...
Page 135
... Name Type Reset value = 00000000 Bit Name 7:0 fhs[7:0] Frequency Hopping Step Size in 10 kHz Increments. See formula for the nominal carrier frequency at "Register 76h. Nominal Carrier Fre- quency" fhch[7:0] R/W Function fhs[7:0] R/W Function Preliminary Rev 0.2 Si4330 135 ...
Page 136
... Si4330 Register 7Bh. Turn Around and 15.4 Length Compliance Bit D7 D6 15.4 Length Name R/W Type Reset value = 01111011 Bit Name 7 15.4 Length 15.4 Packet Length Compliance. If set, then PK Length definition for both TX and RX will also include the CRC bytes, If reset, then the Length refers ONLY to the DATA payload. For example, writing “9” to this register when it is set, means we are sending/expecting “ ...
Page 137
... Register 7Fh. FIFO Access Bit D7 D6 Name Type Reset value = NA Bit Name 7:0 fifod[7:0] FIFO Data. A Read (R this address will begin a burst read of the RX FIFO fifod[7:0] R/W Function Preliminary Rev 0.2 Si4330 137 ...
Page 138
... PADDLE_GND GND The exposed metal paddle on the bottom of the Si4330 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4330. ...
Page 139
... Ordering Information Part Number* Si4330-A0-FM ISM EZRadioPRO Receiver *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. Description Preliminary Rev 0.2 Si4330 Package Operating Type Temperature QFN-20 – °C Pb-free 139 ...
Page 140
... Si4330 15. Package Information Figure 34 illustrates the package details for the Si4330, and Figure 35 illustrates the landing pattern details. Figure 34. QFN-20 Package Dimensions Figure 35. QFN-20 Landing Pattern Dimensions 140 Preliminary Rev 0.2 ...
Page 141
... OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated register descriptions Preliminary Rev 0.2 Si4330 141 ...
Page 142
... Si4330 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: wireless@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...