si4330 Silicon Laboratories, si4330 Datasheet - Page 34

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Si4330
6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access
Control" through “Register 39h. Synchronization Word 0,” on page 107 and “Register 3Fh. Check Header 3,” on
page 108 through “Register 4Bh. Received Packet Length,” on page 112 control the configuration, status, and
decoded RX packet data for Packet Handling.
The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a one. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
Data
CRC
Preamble
1-512 Bytes
1-4 Bytes
0 or 2
Bytes
Figure 12. Packet Structure
An overview of the packet handler configuration registers is shown in Table 13. A complete register description can
be found in “12.1. Complete Register Table and Descriptions”.
6.3. Packet Handler RX Mode
6.3.1. Packet Handler Disabled
When the packet handler is disabled certain portions of the packet handler are still required. Proper modem
operation requires preamble and sync, as shown in Figure 13. Bits after sync will be treated as raw data with no
qualification. This mode allows for the creation of a custom packet handler when the automatic qualification
parameters are not sufficient. Manchester encoding is supported but the use of data whitening, CRC, or header
checks is not.
Preamble
SYNC
DATA
Figure 13. Required RX Packet Structure with Packet Handler Disabled
6.3.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. If multiple packets
are desired to be stored in the FIFO, then there are options available for the different fields that will be stored into
the FIFO. Figure 14 demonstrates the options and settings available when multiple packets are enabled. Figure 15
demonstrates the operation of fixed packet length and correct/incorrect packets.
34
Preliminary Rev 0.2